A semiconductor device, a method of manufacturing the same and an electronic device including the semiconductor device are provided. According to embodiments, the semiconductor device may include a substrate, a first source/drain layer, a channel layer and a second source/drain layer stacked in sequence on the substrate, and a gate stack surrounding a periphery of the channel layer. The channel layer includes a channel region close to its peripheral surface and a body region disposed on an inner side of the channel region.

A manufacturing method of an HEMT includes: forming a heterostructure; forming a first gate layer of intrinsic semiconductor material on the heterostructure; forming a second gate layer, containing dopant impurities of a P type, on the first gate layer; removing first portions of the second gate layer so that second portions, not removed, of the second gate layer form a doped gate region; and carrying out a thermal annealing of the doped gate region so as to cause a diffusion of said dopant impurities of the P type in the first gate layer and in the heterostructure, with a concentration, in the heterostructure, that decreases as the lateral distance from the doped gate region increases.

A semiconductor structure is provided that contains a non-volatile battery which controls gate bias and has increased output voltage retention and voltage resolution. The semiconductor structure may include a semiconductor substrate including at least one channel region that is positioned between source/drain regions. A gate dielectric material is located on the channel region of the semiconductor substrate. A battery stack is located on the gate dielectric material. The battery stack includes, a cathode current collector located on the gate dielectric material, a cathode material located on the cathode current collector, a first ion diffusion barrier material located on the cathode material, an electrolyte located on the first ion diffusion barrier material, a second ion diffusion barrier material located on the electrolyte, an anode region located on the second ion diffusion barrier material, and an anode current collector located on the anode region.

A method for manufacturing a semiconductor device having a edge termination region comprises a stacking process, an ion implantation process, and a heat treatment process. In the stacking process, a p-type semiconductor layer containing a p-type impurity is stacked on an n-type semiconductor layer containing an n-type impurity. In the ion implantation process, at least one of the n-type impurity and the p-type impurity is ion-implanted into the p-type semiconductor layer located in the edge termination region. The ion implantation process and the heat treatment process are performed such that the p-type impurity of the p-type semiconductor layer is diffused into the n-type semiconductor layer to form a p-type impurity containing region in at least part of the n-type semiconductor layer and below a region of the p-type semiconductor layer into which the ion implantation has been performed.

A high electron mobility transistor (HEMT) includes a silicon substrate, an unintentionally doped gallium nitride (UID GaN) layer over the silicon substrate. The HEMT further includes a donor-supply layer over the UID GaN layer, a gate structure, a drain, and a source over the donor-supply layer. The HEMT further includes a dielectric layer having one or more dielectric plug portions in the donor-supply layer and top portions between the gate structure and the drain over the donor-supply layer. A method for making the HEMT is also provided.

A semiconductor device includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a source/drain pair, a fluorinated region, and a gate. The channel layer is disposed over the substrate. The barrier layer is disposed over the channel layer. The compound semiconductor layer is disposed over the barrier layer. The source/drain pair is disposed over the substrate, wherein the source and the drain are located on opposite sides of the compound semiconductor layer. The fluorinated region is disposed in the compound semiconductor layer. The gate is disposed on the compound semiconductor layer.

An enhanced symmetric multicycle rapid thermal annealing process for removing defects and activating implanted dopant impurities in a III-nitride semiconductor sample. A sample is placed in an enclosure and heated to a temperature T.sub.1 under an applied pressure P.sub.1 for a time t.sub.1. While the heating of the sample is maintained, the sample is subjected to a series of rapid laser irradiations under an applied pressure P.sub.2 and a baseline temperature T.sub.2. Each of the laser irradiations heats the sample to a temperature T.sub.max above its thermodynamic stability limit. After a predetermined number of temperature pulses or a predetermined period of time, the laser irradiations are stopped and the sample is brought to a temperature T.sub.3 and held at T.sub.3 for a time t.sub.3 to complete the annealing.

Semiconductor devices having metallic source and drain regions are described. For example, a semiconductor device includes a gate electrode stack disposed above a semiconducting channel region of a substrate. Metallic source and drain regions are disposed above the substrate, on either side of the semiconducting channel region. Each of the metallic source and drain regions has a profile. A first semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic source region, and conformal with the profile of the metallic source region. A second semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic drain region, and conformal with the profile of the metallic drain region.

An n-type GaN layer, a p-type diffusion region formed by ion implantation and annealing in a part of the n-type layer, and a Schottky electrode are formed on the n-type layer. A region without the p-type region is defined as region A, and a region with the p-type region is defined as region B. In region A, an average density of each electron trap level of the n-type layer in a region having a depth of 0.8 m to 1.6 m on the n-type layer side is set so as to satisfy the predetermined conditions. In region B, an average density of each carrier trap level of the n-type layer in a region having a depth of 0.8 m to 1.6 m on the n-type layer side from a boundary between the n-type layer and the p-type diffusion region is set so as to satisfy the predetermined conditions.

Fabrication of doped AlN crystals and/or AlGaN epitaxial layers with high conductivity and mobility is accomplished by, for example, forming mixed crystals including a plurality of impurity species and electrically activating at least a portion of the crystal.