The invention belongs to the technical field of semiconductor material preparation, and in particular provides a preparation method of tin doped n-type gallium oxide. To pre-deposit the appropriate tin doping source on gallium oxide materials in proper ways. The gallium oxide material is then placed in a high temperature tube in an appropriate manner. Then the tin atoms can be controlled to diffuse into the gallium oxide material by heat treatment at a certain temperature for a period of time. Then the tin atoms can be activated as an effective donor to realize the n-type doping of the gallium oxide material. In this invention, the doping can be realized after the preparation of the gallium oxide material is completed, and the necessary equipment and process are simple, and the doping controllability is high. The tin doping technique can not only fabricate the vertical structure device based on the n-type gallium oxide material, but also fabricate the transverse device structure and integrate various devices, so as to develop a new gallium oxide-based device which cannot be fabricated by the traditional doping technique.

An n-type GaN layer, a p-type diffusion region formed by ion implantation and annealing in a part of the n-type layer, and a Schottky electrode are formed on the n-type layer. A region without the p-type region is defined as region A, and a region with the p-type region is defined as region B. In region A, an average density of each electron trap level of the n-type layer in a region having a depth of 0.8 m to 1.6 m on the n-type layer side is set so as to satisfy the predetermined conditions. In region B, an average density of each carrier trap level of the n-type layer in a region having a depth of 0.8 m to 1.6 m on the n-type layer side from a boundary between the n-type layer and the p-type diffusion region is set so as to satisfy the predetermined conditions.

A method of forming a doped gallium nitride (GaN) layer includes providing a substrate structure, including a gallium nitride layer, forming a dopant source layer over the gallium nitride layer, and depositing a capping structure over the dopant source layer. The method also includes annealing the substrate structure to diffuse dopants into the gallium nitride layer, removing the capping structure and the dopant source layer, and activating the diffused dopants.

Various embodiments provide a method of reducing a sheet resistance in an electronic device encapsulated at least partially in an encapsulation material, wherein the method comprises: providing an electronic device comprising a multilayer structure and being at least partially encapsulated by an encapsulation material; and locally introducing energy into the multilayer structure for reducing a sheet resistance.

A semiconductor structure is provided that contains a non-volatile battery which controls gate bias and has increased output voltage retention and voltage resolution. The semiconductor structure may include a semiconductor substrate including at least one channel region that is positioned between source/drain regions. A gate dielectric material is located on the channel region of the semiconductor substrate. A battery stack is located on the gate dielectric material. The battery stack includes, a cathode current collector located on the gate dielectric material, a cathode material located on the cathode current collector, a first ion diffusion barrier material located on the cathode material, an electrolyte located on the first ion diffusion barrier material, a second ion diffusion barrier material located on the electrolyte, an anode region located on the second ion diffusion barrier material, and an anode current collector located on the anode region.

A method of processing semiconductor material includes applying an organosulfur solution to a top surface of a semiconductor material, the organosulfur solution having at least one organosulfur compound. The at least one organosulfur compound has at least one sulfur atom double bonded to a carbon atom and a pH of not less than 8. An organosulfur solution may be applied at temperatures above 25 C. to increase sulfur deposition rates and increase sulfur coverage on a surface of a semiconductor material.

Monolithic finFETs including a majority carrier channel in a first III-V compound semiconductor material disposed on a second III-V compound semiconductor. While a mask, such as a sacrificial gate stack, is covering the channel region, a source of an amphoteric dopant is deposited over exposed fin sidewalls and diffused into the first III-V compound semiconductor material. The amphoteric dopant preferentially activates as a donor within the first III-V material and an acceptor with the second III-V material, providing transistor tip doping with a p-n junction between the first and second III-V materials. A lateral spacer is deposited to cover the tip portion of the fin. Source/drain regions in regions of the fin not covered by the mask or spacer electrically couple to the channel through the tip region. The channel mask is replaced with a gate stack.

A semiconductor device including a first source/drain region at a lower portion thereof, a second source/drain region at an upper portion thereof, a channel region between the first source/drain region and the second source/drain region and close to peripheral surfaces thereof, and a body region inside the channel region. The semiconductor device may further include a gate stack formed around a periphery of the channel region.

A semiconductor device including a substrate, a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, and a gate stack surrounding a periphery of the channel layer. The channel layer includes a semiconductor material causing an increased ON current and/or a reduced OFF current as compared to Si.

In one embodiment, a product includes a structure comprising a material of a Group-III-nitride having a dopant, where a concentration of the dopant in the structure has a concentration gradient characteristic of diffusion of the dopant inward from at least a portion of a surface of the structure in a direction substantially normal to the portion of the surface. The structure has less than 1% decomposition of the Group-III-nitride at the surface of the structure.