The invention relates to a method for producing a semiconductor component comprising performing a plasma treatment of an exposed surface of a semiconductor material with halogens, and carrying out a diffusion method with dopants on the exposed surface.

Disclosed are a semiconductor structure and a preparation method thereof. The semiconductor structure includes a substrate, including a first region arranged at the center of the substrate and a second region arranged at the periphery of the first region; and a composite buffer layer arranged on the substrate, including a carbon-containing first buffer layer including at least one set of a first sub-buffer layer and a second sub-buffer layer stacked in layers; therein, a carbon concentration of the first sub-buffer layer arranged at the first region is higher than that arranged at the second region; and a carbon concentration of the second sub-buffer layer arranged at the first region is lower than that at arranged the second region. Therefore, uniformity of the carbon concentration of the composite buffer layer is improved to improve resistivity of the composite buffer layer, so as to increase breakdown voltage and improve device performance.

A semiconductor device includes a first and a second nitride-based semiconductor layers, a first p-type doped nitride-based semiconductor layer, a first and a second electrodes. The first p-type doped nitride-based semiconductor layer is disposed above the second nitride-based semiconductor layer and has a bottom surface in contact with the second nitride-based semiconductor layer. The first p-type doped nitride-based semiconductor layer has a hydrogen concentration which decrementally decreases along a direction pointing from the bottom surface toward a top surface of the first p-type doped nitride-based semiconductor layer. The first electrode is disposed on the first p-type doped nitride-based semiconductor layer and in contact with the top surface of the first p-type doped nitride-based semiconductor layer. The second electrode is disposed above the second nitride-based semiconductor layer to define a drift region.

An apparatus, in accordance with one embodiment, includes a superjunction device having a voltage sustaining layer formed of a semiconductor material and a dopant in the voltage sustaining layer. The dopant is for distributing an electric field within the voltage sustaining layer. The dopant is more concentrated along a sidewall of the voltage sustaining layer than toward a center of the voltage sustaining layer, the sidewall extending at least a portion of the distance between a top surface and a bottom surface of a voltage sustaining layer. Methods of electric field-enhanced dopant diffusion to form a superjunction device are also presented.

An enhanced symmetric multicycle rapid thermal annealing process for removing defects and activating implanted dopant impurities in a III-nitride semiconductor sample. A sample is placed in an enclosure and heated to a temperature T.sub.1 under an applied pressure P.sub.1 for a time t.sub.1. While the heating of the sample is maintained, the sample is subjected to a series of rapid laser irradiations under an applied pressure P.sub.2 and a baseline temperature T.sub.2. Each of the laser irradiations heats the sample to a temperature T.sub.max above its thermodynamic stability limit. After a predetermined number of temperature pulses or a predetermined period of time, the laser irradiations are stopped and the sample is brought to a temperature T.sub.3 and held at T.sub.3 for a time t.sub.3 to complete the annealing.

A technique for selective-area diffusion doping of III-N epitaxial material layers and for fabricating power device structures utilizing this technique. Dopant species such as Mg are introduced into the III-N material layer and are diffused into the III-N material by annealing under stable or metastable conditions. The dopant species can be introduced via deposition of a metal or alloy layer containing such species using sputtering, e-beam evaporation or other technique known to those skilled in the art. The dopant material layer is capped with a thermally stable layer to prevent decomposition and out-diffusion, and then is annealed under stable or metastable conditions to diffuse the dopant into the III-N material GaN without decomposing the surface.

There are provided an Integrated Circuit (IC) unit, a method of manufacturing the same, and an electronic device including the IC unit. According to an embodiment, the IC unit includes a first source/drain layer, a channel layer and a second source/drain layer for a first device and a first source/drain layer, a channel layer and a second source/drain layer for a second device stacked in sequence on a substrate. In the first device, the channel layer includes a first portion and a second portion separated from each other. The first source/rain layer and the second source/drain layer each extend integrally to overlap both the first portion and the second portion of the channel layer. The IC unit further includes a first gate stack surrounding a periphery of the first portion and also a periphery of the second portion of the channel layer of the first device, and a second gate stack surrounding a periphery of the channel layer of the second device.

There are provided a semiconductor device, a method of manufacturing the same, and an electronic device including the device. According to an embodiment, the semiconductor device may include a substrate, and a first device and a second device formed on the substrate. Each of the first device and the second device includes a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, and also a gate stack surrounding a periphery of the channel layer. The channel layer of the first device and the channel layer of the second device are substantially co-planar with each other, and the respective second source/drain layers of the first device and the second device are stressed differently.

An active cell region, an edge termination region surrounding the active cell region and an intermediate region located at an intermediate position between these regions are provided, the active cell region has a trench gate type MOS structure on a top side, and a vertical structure on a bottom side includes a p-collector layer, an n-buffer layer on the p-collector layer, and an n-drift layer on the n-buffer layer, the n-buffer layer has a first buffer portion provided on the p-collector layer side, and a second buffer portion provided on the n-drift layer side, the peak impurity concentration of the first buffer portion is higher than the peak impurity concentration of the second buffer portion, and the impurity concentration gradient on the n-drift layer side of the second buffer portion is gentler than the impurity concentration gradient on the n-drift layer side of the first buffer portion.

A semiconductor device includes a codoped layer, a channel layer, a barrier layer, and a gate electrode disposed in a trench extending through the barrier layer and reaching a middle point in the channel layer via a gate insulating film. On both sides of the gate electrode, a source electrode and a drain electrode are formed. On the source electrode side, an n-type semiconductor region is disposed to fix a potential and achieve a charge removing effect while, on the drain electrode side, a p-type semiconductor region is disposed to improve a drain breakdown voltage. By introducing hydrogen into a region of the codoped layer containing Mg as a p-type impurity in an amount larger than that of Si as an n-type impurity where the n-type semiconductor region is to be formed, it is possible to inactivate Mg and provide the n-type semiconductor region.