Embodiments of the present disclosure provide methods for forming conductive lines with dielectric cut features. Particularly, embodiments of present disclosure provide a method for forming conductive line pattern using two patterning processes. A line pattern is formed in the first patterning process. A cut pattern is formed over the line pattern in the second patterning process. The cut pattern is formed by forming cut openings with a width smaller than the line width of the line pattern and then filling the cut opening with a mask material.

Systems and approaches for fabricating an integrated circuit structure including a metal layer formed using a beam of low energy atoms are described. In an example, a system for fabricating an integrated circuit structure includes a sample holder for supporting a 300 mm wafer facing down, the substrate having a feature thereon. The system also includes a source for providing a beam of low energy metal atoms to form a metal layer on the feature of the substrate. The system also includes a source of gas atoms for controlling the texture of the layer

According to various embodiments, a transistor device may include a semiconductor structure having a trench formed therein. The semiconductor structure may include a buffer layer and a barrier layer arranged over the buffer layer. The trench may extend at least to the buffer layer. The transistor device may include a source terminal, a drain terminal, and a gate terminal arranged between the source terminal and the drain terminal. The gate terminal may extend into the trench. The transistor device may include an electrode component. The electrode component may include an electrode. The electrode component may extend into the trench where the electrode component is separated from the gate terminal. The electrode component may contact a side wall of the trench.

A high electron mobility transistor (HEMT) includes a group III-V channel layer, a passivation layer, a group III-V barrier layer, a gate structure, and a source/drain electrode. The passivation layer is disposed on the group III-V channel layer and includes a gate contact hole and a source/drain contact hole, and the group III-V barrier layer is disposed between the group III-V channel layer and the passivation layer. The gate structure includes group III-V gate layer, a gate etch stop layer, and a gate electrode which are stacked in sequence. The gate electrode is disposed in the gate contact hole and conformally covers a portion of the top surface of the passivation layer. The source/drain electrode is disposed in the source/drain contact hole and conformally covers another portion of the top surface of the passivation layer.

A gate insulator film made of silicon dioxide or gallium oxide is formed on a gallium nitride (GaN) substrate. The GaN substrate is preheated by irradiation with light from halogen lamps, and the surface of the substrate including the gate insulator film is heated to a high temperature for an extremely short time by irradiation with a flash of light from flash lamps. Heating the substrate surface including the gate insulator film in an extremely short heat treatment time prevents the desorption of nitrogen from GaN and makes it possible to reduce the traps existing at the interface between the gate insulator film and GaN without diffusing gallium into the gate insulator film.

A method of forming a semiconductor device that includes forming a metal oxide material on a III-V semiconductor channel region or a germanium containing channel region; and treating the metal oxide material with an oxidation process. The method may further include depositing of a hafnium containing oxide on the metal oxide material after the oxidation process, and forming a gate conductor atop the hafnium containing oxide. The source and drain regions are on present on opposing sides of the gate structure including the metal oxide material, the hafnium containing oxide and the gate conductor.

A semiconductor crystal substrate includes a crystal substrate that is formed of a material including GaSb or InAs, a first buffer layer that is formed on the crystal substrate and formed of a material including GaSb, the first buffer layer having n-type conductivity, and a second buffer layer that is formed on the first buffer layer and formed of a material including GaSb, the second buffer layer having p-type conductivity.

An HEMT device of a normally-on type, comprising a heterostructure; a dielectric layer extending over the heterostructure; and a gate electrode extending right through the dielectric layer. The gate electrode is a stack, which includes: a protection layer, which is made of a metal nitride with stuffed grain boundaries and extends over the heterostructure, and a first metal layer, which extends over the protection layer and is completely separated from the heterostructure by said protection layer.

Embodiments include a first nanowire transistor having a first source and a first drain with a first channel in between, where the first channel includes a first III-V alloy. A first gate stack is around the first channel, where a portion of the first gate stack is between the first channel and a substrate. The first gate stack includes a gate electrode metal in contact with a gate dielectric. A second nanowire transistor is on the substrate, having a second source and a second drain with a second channel therebetween, the second channel including a second III-V alloy. A second gate stack is around the second channel, where an intervening material is between the second gate stack and the substrate, the intervening material including a third III-V alloy. The second gate stack includes the gate electrode metal in contact with the gate dielectric.

A semiconductor diode includes an engineered substrate including a substantially single crystal layer, a buffer layer coupled to the substantially single crystal layer, and a semi-insulating layer coupled to the buffer layer. The semiconductor diode also includes a first N-type gallium nitride layer coupled to the semi-insulating layer and a second N-type gallium nitride layer coupled to the first N-type gallium nitride layer. The first N-type gallium nitride layer has a first doping concentration and the second N-type gallium nitride layer has a second doping concentration less than the first doping concentration. The semiconductor diode further includes a P-type gallium nitride layer coupled to the second N-type gallium nitride layer, an anode contact coupled to the P-type gallium nitride layer, and a cathode contact coupled to a portion of the first N-type gallium nitride layer.