Patent classifications
H01L21/285
SURFACE PROFILING AND TEXTURING OF CHAMBER COMPONENTS
Methods and apparatus for surface profiling and texturing of chamber components for use in a process chamber, such surface-profiled or textured chamber components, and method of use of same are provided herein. In some embodiments, a method includes measuring a parameter of a reference substrate or a heated pedestal using one or more sensors and modifying a surface of a chamber component physically based on the measured parameter.
SEMICONDUCTOR MANUFACTURING METHOD AND SEMICONDUCTOR MANUFACTURING APPARATUS
A semiconductor manufacturing method using a semiconductor manufacturing apparatus 100 including a treating chamber 1, the method including: a first process of supplying a complexing gas into the treating chamber in which a wafer 2 having a surface having a transition metal-containing film formed thereon is placed, to adsorb an organic compound as a component of the complexing gas to the transition metal-containing film, the transition metal-containing film containing a transition metal element; and a second process of heating the wafer in which the organic compound is adsorbed to the transition metal-containing film, to react the organic compound with the transition metal element, thereby converting the organic compound into an organometallic complex, and desorbing the organometallic complex, wherein the organic compound has Lewis basicity, and is a multidentate ligand molecule capable of forming a bidentate or more coordination bond with the transition metal element.
IC with 3D metal-insulator-metal capacitor
An integrated circuit (IC) including a semiconductor surface layer of a substrate including functional circuitry having circuit elements formed in the semiconductor surface layer configured together with a Metal-Insulator-Metal capacitor (MIM) capacitor on the semiconductor surface layer for realizing at least one circuit function. The MIM capacitor includes a multilevel bottom capacitor plate having an upper top surface, a lower top surface, and sidewall surfaces that connect the upper and lower top surfaces (e.g., a bottom plate layer on a three-dimensional (3D) layer or the bottom capacitor plate being a 3D bottom capacitor plate). At least one capacitor dielectric layer is on the bottom capacitor plate. A top capacitor plate is on the capacitor dielectric layer, and there are contacts through a pre-metal dielectric layer to contact the top capacitor plate and the bottom capacitor plate.
Adjusting the Profile of Source/Drain Regions to Reduce Leakage
A method includes forming a protruding semiconductor stack including a plurality of sacrificial layers and a plurality of nanostructures, with the plurality of sacrificial layers and the plurality of nanostructures being laid out alternatingly. The method further includes forming a dummy gate structure on the protruding semiconductor stack, etching the protruding semiconductor stack to form a source/drain recess, and forming a source/drain region in the source/drain recess. The formation of the source/drain region includes growing first epitaxial layers. The first epitaxial layers are grown on sidewalls of the plurality of nanostructures, and a cross-section of each of the first epitaxial layers has a quadrilateral shape. The first epitaxial layers have a first dopant concentration. The formation of the source/drain region further includes growing a second epitaxial layer on the first epitaxial layers. The second epitaxial layer has a second dopant concentration higher than the first dopant concentration.
FILM DEPOSITION METHOD AND ELEMENT INCLUDING FILM DEPOSITED BY THE FILM DEPOSITION METHOD
A film deposition method may include preparing a non-planar substrate including a first surface, a second surface, and an inclined surface between the first surface and the second surface; depositing a film having a thickness deviation on the first surface, the second surface, and the inclined surface; and etching the film deposited on the first surface, the second surface, and the inclined surface. A height of the second surface may be different than a height of the first surface.
HEATING DEVICE AND SEMICONDUCTOR PROCESSING APPARATUS
A heating device includes a heating assembly. The heating assembly includes a ventilation structure configured to blow gas to an edge of a to-be-processed workpiece carried by the heating device. The heating device further includes a base arranged on a side of the heating assembly away from a heating surface of the heating assembly. A mounting space is formed between the base and the heating assembly. The heating device also includes a cooling mechanism arranged in the mounting space, located at a position corresponding to an edge area of the heating surface, and configured to cool the heating assembly.
TEMPERATURE-CONTROLLED SURFACE WITH A CRYO-NANOMANIPULATOR FOR IMPROVED DEPOSITION RATE
A method of depositing material over a sample in a deposition region of the sample with a charged particle beam column, the method comprising: positioning a sample within a vacuum chamber such that the deposition region is under a field of view of the charged particle beam column; cooling the deposition region by contacting the sample with a cyro-nanomanipulator tool in an area adjacent to the deposition region; injecting a deposition precursor gas into the vacuum chamber at a location adjacent to the deposition region; generating a charged particle beam with a charged particle beam column and focusing the charged particle beam on the sample; and scanning the focused electron beam across the localized region of the sample to activate molecules of the deposition gas that have adhered to the sample surface in the deposition region and deposit material on the sample within the deposition region
Low resistance source drain contact formation with trench metastable alloys and laser annealing
Techniques for forming a metastable phosphorous P-doped silicon Si source drain contacts are provided. In one aspect, a method for forming n-type source and drain contacts includes the steps of: forming a transistor on a substrate; depositing a dielectric over the transistor; forming contact trenches in the dielectric that extend down to source and drain regions of the transistor; forming an epitaxial material in the contact trenches on the source and drain regions; implanting P into the epitaxial material to form an amorphous P-doped layer; and annealing the amorphous P-doped layer under conditions sufficient to form a crystalline P-doped layer having a homogenous phosphorous concentration that is greater than about 1.5×10.sup.21 atoms per cubic centimeter (at./cm.sup.3). Transistor devices are also provided utilizing the present P-doped Si source and drain contacts.
SUBSTRATE PROCESSING METHOD, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM AND SUBSTRATE PROCESSING APPARATUS
There is provided a technique that includes: (a) adjusting a temperature of a substrate to a first temperature; (b) forming a first molybdenum-containing film on the substrate by performing: (b1) supplying a molybdenum-containing gas to the substrate; and (b2) supplying a reducing gas to the substrate for a first time duration; (c) adjusting the temperature of the substrate to a second temperature after performing (b); and (d) forming a second molybdenum-containing film on the first molybdenum-containing film by performing: (d1) supplying the molybdenum-containing gas to the substrate; and (d2) supplying the reducing gas to the substrate for a second time duration.
Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium
There is provided a technique that includes selectively doping a metal film with a dopant by performing: supplying a dopant-containing gas containing the dopant to a substrate in which the metal film and a film other than the metal film are formed on a film in which the dopant is doped; and removing the dopant-containing gas from above the substrate.