A display device includes a substrate, a first transistor, a second transistor and a conductive connection portion disposed on the substrate. The first transistor is electrically connected to the gate electrode of the second transistor through the conductive connection portion. An insulating layer is disposed on the conductive connection portion.

A pixel electrode is disposed on the insulating layer and is electrically connected to the second transistor. The pixel electrode is at least partially overlapped with the conductive connection portion. A light-emitting element is disposed on the pixel electrode. The conductive connection portion and the pixel electrode form a capacitor. The capacitor has an equivalent permittivity and a thickness. The ratio of the equivalent permittivity to the thickness is in a range from 0.4*(1E+5)F/m̂2 to 296.48*(1E+5)F/m̂2.

A display device includes a substrate, a first transistor, a second transistor and a conductive connection portion disposed on the substrate. The first transistor is electrically connected to the gate electrode of the second transistor through the conductive connection portion. An insulating layer is disposed on the conductive connection portion.

A pixel electrode is disposed on the insulating layer and is electrically connected to the second transistor. The pixel electrode is at least partially overlapped with the conductive connection portion. A light-emitting element is disposed on the pixel electrode. The conductive connection portion and the pixel electrode form a capacitor. The capacitor has an equivalent permittivity and a thickness. The ratio of the equivalent permittivity to the thickness is in a range from 0.4*(1E+5)F/m̂2 to 296.48*(1E+5)F/m̂2.

Structures and methods for direct bonding are disclosed. A bonded structure can include a first element and a second element. The first element can include a first non-conductive structure that has a non-conductive bonding surface, a cavity that extends at least partially through a thickness of the non-conductive structure from the non-conductive bonding surface, and a first conductive feature that has a first conductive material and a second conductive material over the first conductive material disposed in the cavity. A maximum grain size, in a linear lateral dimension, of the second conductive material can be smaller than 20% of the linear lateral dimension of the conductive feature. There can be less than 20 parts per million (ppm) of impurities at grain boundaries of the second conductive material.

A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A patterned dielectric layer with a plurality of openings is formed on the substrate. A barrier layer is deposited in the openings by a first tool and a sacrificing protection layer is deposited on the barrier layer by the first tool. The sacrificing layer is removed and a metal layer is deposited on the barrier layer by a second tool.

A system and method for providing a conductive line is provided. In an embodiment the conductive line is formed by forming two passivation layers, wherein each passivation layer is independently patterned. Once formed, a seed layer is deposited into the two passivation layers, and a conductive material is deposited to fill and overfill the patterns within the two passivation layers. A planarization process such as a chemical mechanical polish may then be utilized in order to remove excess conductive material and form the conductive lines within the two passivation layers.

In accordance with one embodiment of the present disclosure, a method for depositing metal on a reactive metal film on a workpiece includes electrochemically depositing a metallization layer on a seed layer formed on a workpiece using a plating electrolyte having at least one plating metal ion, a pH range of about 6 to about 11 and applying a cathodic potential in the range of about −1 V to about −6 V. The workpiece includes a barrier layer disposed between the seed layer and a dielectric surface of the workpiece, the barrier layer including a first metal having a standard electrode potential more negative than 0 V and the seed layer including a second metal having a standard electrode potential more positive than 0 V.

A device comprises a base element and a metallization layer over the base element. The metallization layer comprises pores and has a varying degree of porosity, the degree of porosity being higher in a portion adjacent to the base element than in a portion remote from the base element.

A device comprises a base element and a metallization layer over the base element. The metallization layer comprises pores and has a varying degree of porosity, the degree of porosity being higher in a portion adjacent to the base element than in a portion remote from the base element.

A method of forming a transistor device is provided. The method includes forming a plurality of gate structures including a gate spacer and a gate electrode on a substrate, wherein the plurality of gate structures are separated from each other by a source/drain contact. The method further includes reducing the height of the gate electrodes to form gate troughs, and forming a gate liner on the gate electrodes and gate spacers. The method further includes forming a gate cap on the gate liner, and reducing the height of the source/drain contacts between the gate structures to form a source/drain trough. The method further includes forming a source/drain liner on the source/drain contacts and gate spacers, wherein the source/drain liner is selectively etchable relative to the gate liner, and forming a source/drain cap on the source/drain liner.

An integrated circuit (IC) with an impedance sensor fabricated on a surface of the substrate is disclosed. The impedance sensor includes a bottom conductive plate formed on the substrate. A sensing membrane is formed on the bottom conductive plate. A top conductive plate is formed on the sensing membrane, in which the top conductive plate is a fusion of conductive nanoparticles having a random three dimensional porosity that is permeable to a reagent.