A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.

A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.

An electroplating apparatus for electroplating metal on a substrate includes a plating chamber configured to contain an electrolyte, a substrate holder configured to hold and rotate the substrate during electroplating, an anode, and an azimuthally asymmetric auxiliary electrode configured to be biased both anodically and cathodically during electroplating. The azimuthally asymmetric auxiliary electrode (which may be, for example, C-shaped), can be used for controlling azimuthal uniformity of metal electrodeposition by donating and diverting ionic current at a selected azimuthal position. In another aspect, an electroplating apparatus for electroplating metal includes a plating chamber configured to contain an electrolyte, a substrate holder configured to hold and rotate the substrate during electroplating, an anode, a shield configured to shield current at the periphery of the substrate; and an azimuthally asymmetric auxiliary anode configured to donate current to the shielded periphery of the substrate at a selected azimuthal position on the substrate.

A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.

A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.

Nanotwinned copper and non-nanotwinned copper may be electroplated to form mixed crystal structures such as 2-in-1 copper via and RDL structures or 2-in-1 copper via and pillar structures. Nanotwinned copper may be electroplated on a non-nanotwinned copper layer by pretreating a surface of the non-nanotwinned copper layer with an oxidizing agent or other chemical reagent. Alternatively, nanotwinned copper may be electroplated to partially fill a recess in a dielectric layer, and non-nanotwinned copper may be electroplated over the nanotwinned copper to fill the recess. Copper overburden may be subsequently removed.

According to an embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type, a first metal portion, a third semiconductor region of a second conductivity type, a first electrode, a fourth semiconductor region of the second conductivity type, and a second electrode. The first semiconductor region includes a first portion and a second portion. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on part of the second semiconductor region. The first metal portion is provided in the first semiconductor region. The third semiconductor region is positioned on the first portion. The fourth semiconductor region is provided on another part of the second semiconductor region. The fourth semiconductor region is separated from the third semiconductor region. The fourth semiconductor region is positioned on the second portion.

An electrolytic processing jig configured to perform an electrolytic processing on a processing target substrate includes a base body having a flat plate shape; an electrode provided at the base body; three or more terminals provided at the base body, each having elasticity and configured to be brought into contact with a peripheral portion of the processing target substrate; and a detecting unit configured to electrically detect a contact of at least one of the terminals with the processing target substrate.

A substrate liquid processing method includes holding a substrate W with a substrate holder 52; supplying a plating liquid L1 onto a top surface of the substrate; covering the substrate with a cover body 6 disposed above the held substrate, the cover body having a ceiling portion 61; and heating the plating liquid on the substrate by a heating unit 63 provided in either one of at least the cover body and the substrate holder in a state that the substrate is covered with the cover body. A gas exhausting operation of pushing out a reaction gas staying between the cover body and the substrate by moving either one of at least the cover body and the substrate holder vertically is performed in the heating of the plating liquid.

A substrate liquid processing method includes holding a substrate W with a substrate holder 52; supplying a plating liquid L1 onto a top surface of the substrate; covering the substrate with a cover body 6 disposed above the held substrate, the cover body having a ceiling portion 61; and heating the plating liquid on the substrate by a heating unit 63 provided in either one of at least the cover body and the substrate holder in a state that the substrate is covered with the cover body. A gas exhausting operation of pushing out a reaction gas staying between the cover body and the substrate by moving either one of at least the cover body and the substrate holder vertically is performed in the heating of the plating liquid.