A structural body according to an embodiment includes a conductive substrate. A main surface of the conductive substrate includes a first region and a second region adjacent to the first region and lower in height than the first region. The first region is provided with one or more recesses having a bottom, a position of which is lower than a position of the second region. A surface region of the conductive substrate on a side of the main surface includes a porous structure at a position between the second region and the one or more recesses.

The present disclosure provides a method of forming a semiconductor device structure. The method includes forming a trench in a dielectric layer on a semiconductor substrate; forming a bottom metal feature of a first metal in a lower portion of the trench by a selective deposition; depositing a barrier layer in an upper portion of the trench, the barrier layer directly contacting both a top surface of the bottom metal feature and sidewalls of the dielectric layer; and forming a top metal feature of a second metal on the barrier layer, filling in the upper portion of the trench, wherein the second metal is different from the first metal in composition.

The present disclosure provides a method of forming a semiconductor device structure. The method includes forming a trench in a dielectric layer on a semiconductor substrate; forming a bottom metal feature of a first metal in a lower portion of the trench by a selective deposition; depositing a barrier layer in an upper portion of the trench, the barrier layer directly contacting both a top surface of the bottom metal feature and sidewalls of the dielectric layer; and forming a top metal feature of a second metal on the barrier layer, filling in the upper portion of the trench, wherein the second metal is different from the first metal in composition.

A semiconductor may include a first inter metal dielectric (IMD) layer, a first blocking layer on the first IMD layer, a metal wiring and a second blocking layer. The first inter metal dielectric (IMD) layer may be formed on a substrate, the first IMD layer may include a low-k material having a dielectric constant lower than a dielectric constant of silicon oxide. The first blocking layer may be formed on the first IMD layer. The first blocking layer may include an oxide having a dielectric constant higher than the dielectric constant of the first IMD layer. The metal wiring may be through the first IMD layer and the first blocking layer. The second blocking layer may be formed on the metal wiring and the first blocking layer. The second blocking layer may include a nitride. The first and second blocking layers may reduce or prevent from the out gassing, so that a semiconductor device may have good characteristics.

A substrate processing apparatus 5 includes a holder 52 (52A), a supply 53 and a cover body 6. The holder 52 (52A) is configured to attract and hold a substrate W. The supply 53 is configured to supply a heated plating liquid to the substrate W attracted to and held by the holder 52 (52A). The cover body 6 is configured to cover the substrate W attracted to and held by the holder 52 (52A), and heat the plating liquid on the substrate W by using a heating device 63 provided in a ceiling member 61 thereof facing a top surface of the substrate W. The holder 52 (52A) includes protrusions 130 projecting from a facing surface 110 thereof facing a bottom surface of the substrate W toward the bottom surface of the substrate W, and each protrusion has a protruding height equal to or larger than 1 mm.

The present disclosure discloses a method for manufacturing an electronic device, including: setting a basic working area; a photoresist coating process; a development process; an etching process; an exposure process; a metal plating process; and a polishing process, wherein the photoresist coating process, the development process, the etching process, the exposure process, the metal plating process and the polishing process respectively have a maximum optimized process area, and a smallest one of the maximum optimized process areas is selected as the basic working area.

A system for printing metal interconnects on a substrate includes an anode substrate. A plurality of anodes are arranged on one side of the anode substrate with a first predetermined gap between adjacent ones of the plurality of anodes. A first plurality of fluid holes have one end located between the plurality of anodes. A plurality of control devices is configured to selectively supply current to the plurality of anodes, respectively. The anode substrate is arranged within a second predetermined gap of a work piece substrate including a metal seed layer. A ratio of the second predetermined gap to the first predetermined gap is in a range from 0.5:1 and 1.5:1. An array controller is configured to energize selected ones of the plurality of anodes using corresponding ones of the plurality of control devices while electrolyte solution is supplied through the first plurality of fluid holes between the anode substrate and the work piece substrate.

A method for forming a through-substrate via structure includes providing a substrate and providing a conductive via structure adjacent to a first surface of the substrate. The method includes providing a recessed region on an opposite surface of the substrate towards the conductive via structure. The method includes providing an insulator in the recessed region and providing a conductive region extending along a first sidewall surface of the recessed region in the cross-sectional view. In some examples, the first conductive region is provided to be coupled to the conductive via structure and to be further along at least a portion of the opposite surface of the substrate outside of the recessed region. The method includes providing a protective structure within the recessed region over a first portion of the first conductive region but not over a second portion of the first conductive region that is outside of the recessed region. The method includes attaching a conductive bump to the second portion of the first conductive region.

A method for forming a through-substrate via structure includes providing a substrate and providing a conductive via structure adjacent to a first surface of the substrate. The method includes providing a recessed region on an opposite surface of the substrate towards the conductive via structure. The method includes providing an insulator in the recessed region and providing a conductive region extending along a first sidewall surface of the recessed region in the cross-sectional view. In some examples, the first conductive region is provided to be coupled to the conductive via structure and to be further along at least a portion of the opposite surface of the substrate outside of the recessed region. The method includes providing a protective structure within the recessed region over a first portion of the first conductive region but not over a second portion of the first conductive region that is outside of the recessed region. The method includes attaching a conductive bump to the second portion of the first conductive region.

Semiconductor dies including ultra-thin wafer backmetal systems, microelectronic devices containing such semiconductor dies, and associated fabrication methods are disclosed. In one embodiment, a method for processing a device wafer includes obtaining a device wafer having a wafer frontside and a wafer backside opposite the wafer frontside. A wafer-level gold-based ohmic bond layer, which has a first average grain size and which is predominately composed of gold, by weight, is sputter deposited onto the wafer backside. An electroplating process is utilized to deposit a wafer-level silicon ingress-resistant plated layer over the wafer-level Au-based ohmic bond layer, while imparting the plated layer with a second average grain size exceeding the first average grain size. The device wafer is singulated to separate the device wafer into a plurality of semiconductor die each having a die frontside, an Au-based ohmic bond layer, and a silicon ingress-resistant plated layer.