A method of forming a three-dimensional (3D) NAND memory device includes: forming a gate line slit through a plurality of alternating layers of an oxide layer and a conductive material layer, where the conductive material layer is further formed on a sidewall and a bottom of the gate line slit; performing an ion implantation process to dope at least a portion of the conductive material layer that is on the bottom and/or a portion of the sidewall of the gate line slit; and performing an etch process in the gate line slit to remove the conductive material layer that is weakened by the ion implantation process.

A thin film transistor of a top-gate-coplanar type includes a source, a drain, a gate, and a semiconductor layer, wherein the semiconductor layer has a first low-resistance region for the source and a second low-resistance region for the drain, wherein the source and the drain are electrically connected through the first low-resistance region, the semiconductor layer, and the second low-resistance region, and wherein the semiconductor layer is formed of an oxide-based semiconductor containing gallium (Ga), zinc (Zn), and tin (Sn).

A thin film transistor of a top-gate-coplanar type includes a source, a drain, a gate, and a semiconductor layer, wherein the semiconductor layer has a first low-resistance region for the source and a second low-resistance region for the drain, wherein the source and the drain are electrically connected through the first low-resistance region, the semiconductor layer, and the second low-resistance region, and wherein the semiconductor layer is formed of an oxide-based semiconductor containing gallium (Ga), zinc (Zn), and tin (Sn).

The instant disclosure includes an implanting apparatus and a method thereof. The implanting apparatus has a chuck configured to carry a substrate is rotated a number of times at an angle during ion implantation. In this way, masks used during semiconductor fabrication is reduced.

The instant disclosure includes an implanting apparatus and a method thereof. The implanting apparatus has a chuck configured to carry a substrate is rotated a number of times at an angle during ion implantation. In this way, masks used during semiconductor fabrication is reduced.

A semiconductor device includes a oxide semiconductor layer provided on an insulating surface and having a channel area, a source area and a drain area sandwiching the channel area, a gate electrode opposite the channel area, and a gate insulating layer provided between the oxide semiconductor layer and the gate electrode, wherein the gate electrode is an oxide conductive layer having the same composition as the oxide semiconductor layer, and the oxide conductive layer includes the same impurity element as the source area and the drain area.

Proton irradiation is performed a plurality of times from rear surface of an n-type semiconductor substrate, which is an n.sup. drift layer, forming an n-type FS layer having lower resistance than the n-type semiconductor substrate in the rear surface of the n.sup. drift layer. When the proton irradiation is performed a plurality of times, the next proton irradiation is performed to as to compensate for a reduction in mobility due to disorder which remains after the previous proton irradiation. In this case, the second or subsequent proton irradiation is performed at the position of the disorder which is formed by the previous proton irradiation. In this way, even after proton irradiation and a heat treatment, the disorder is reduced and it is possible to prevent deterioration of characteristics, such as increase in leakage current. It is possible to form an n-type FS layer including a high-concentration hydrogen-related donor layer.

A semiconductor device includes an extremely thin semiconductor-on-insulator substrate (ETSOI) having a base substrate, a thin semiconductor layer and a buried dielectric therebetween. A device channel is formed in the thin semiconductor layer. Source and drain regions are formed at opposing positions relative to the device channel. The source and drain regions include an n-type material deposited on the buried dielectric within a thickness of the thin semiconductor layer. A gate structure is formed over the device channel.

A semiconductor device includes an extremely thin semiconductor-on-insulator substrate (ETSOI) having a base substrate, a thin semiconductor layer and a buried dielectric therebetween. A device channel is formed in the thin semiconductor layer. Source and drain regions are formed at opposing positions relative to the device channel. The source and drain regions include an n-type material deposited on the buried dielectric within a thickness of the thin semiconductor layer. A gate structure is formed over the device channel.

A change in electrical characteristics in a semiconductor device including an oxide semiconductor film is inhibited, and the reliability is improved. The semiconductor device includes a gate electrode, a first insulating film over the gate electrode, an oxide semiconductor film over the first insulating film, a source electrode electrically connected to the oxide semiconductor film, a drain electrode electrically connected to the oxide semiconductor film, a second insulating film over the oxide semiconductor film, the source electrode, and the drain electrode, a first metal oxide film over the second insulating film, and a second metal oxide film over the first metal oxide film. The first metal oxide film contains at least one metal element that is the same as a metal element contained in the oxide semiconductor film. The second metal oxide film includes a region where the second metal oxide film and the first metal oxide film are mixed.