A memory cell includes a transistor over a semiconductor substrate. The transistor includes a ferroelectric layer arranged along a sidewall of a word line. The ferroelectric layer includes a species with valence of 5, valence of 7, or a combination thereof. An oxide semiconductor layer is electrically coupled to a source line and a bit line. The ferroelectric layer is disposed between the oxide semiconductor layer and the word line.

A memory cell includes a transistor over a semiconductor substrate. The transistor includes a ferroelectric layer arranged along a sidewall of a word line. The ferroelectric layer includes a species with valence of 5, valence of 7, or a combination thereof. An oxide semiconductor layer is electrically coupled to a source line and a bit line. The ferroelectric layer is disposed between the oxide semiconductor layer and the word line.

A method for controlling a concentration of donors in an Al-alloyed gallium oxide crystal structure includes implanting a Group IV element as a donor impurity into the crystal structure with an ion implantation process and annealing the implanted crystal structure to activate the Group IV element to form an electrically conductive region. The method may further include depositing one or more electrically conductive materials on at least a portion of the implanted crystal structure to form an ohmic contact. Examples of semiconductor devices are also disclosed and include a layer of an Al-alloyed gallium oxide crystal structure, at least one region including the crystal structure implanted with a Group IV element as a donor impurity with an ion implantation process and annealed to activate the Group IV element, an ohmic contact including one or more electrically conductive materials deposited on the at least one region.

A method for controlling a concentration of donors in an Al-alloyed gallium oxide crystal structure includes implanting a Group IV element as a donor impurity into the crystal structure with an ion implantation process and annealing the implanted crystal structure to activate the Group IV element to form an electrically conductive region. The method may further include depositing one or more electrically conductive materials on at least a portion of the implanted crystal structure to form an ohmic contact. Examples of semiconductor devices are also disclosed and include a layer of an Al-alloyed gallium oxide crystal structure, at least one region including the crystal structure implanted with a Group IV element as a donor impurity with an ion implantation process and annealed to activate the Group IV element, an ohmic contact including one or more electrically conductive materials deposited on the at least one region.

A semiconductor device is manufactured using a transistor in which an oxide semiconductor is included in a channel region and variation in electric characteristics due to a short-channel effect is less likely to be caused. The semiconductor device includes an oxide semiconductor film having a pair of oxynitride semiconductor regions including nitrogen and an oxide semiconductor region sandwiched between the pair of oxynitride semiconductor regions, a gate insulating film, and a gate electrode provided over the oxide semiconductor region with the gate insulating film positioned therebetween. Here, the pair of oxynitride semiconductor regions serves as a source region and a drain region of the transistor, and the oxide semiconductor region serves as the channel region of the transistor.

A semiconductor device is manufactured using a transistor in which an oxide semiconductor is included in a channel region and variation in electric characteristics due to a short-channel effect is less likely to be caused. The semiconductor device includes an oxide semiconductor film having a pair of oxynitride semiconductor regions including nitrogen and an oxide semiconductor region sandwiched between the pair of oxynitride semiconductor regions, a gate insulating film, and a gate electrode provided over the oxide semiconductor region with the gate insulating film positioned therebetween. Here, the pair of oxynitride semiconductor regions serves as a source region and a drain region of the transistor, and the oxide semiconductor region serves as the channel region of the transistor.

In a method of manufacturing a semiconductor device, a mask layer and a first layer may be sequentially formed on a substrate. The first layer may be patterned by a photolithography process to form a first pattern. A silicon oxide layer may be formed on the first pattern. A coating pattern including silicon may be formed on the silicon oxide layer. The mask layer may be etched using a second pattern as an etching mask to form a mask pattern, and the second pattern may includes the first pattern, the silicon oxide layer and the coating pattern. The mask pattern may have a uniform size.

In a method of manufacturing a semiconductor device, a mask layer and a first layer may be sequentially formed on a substrate. The first layer may be patterned by a photolithography process to form a first pattern. A silicon oxide layer may be formed on the first pattern. A coating pattern including silicon may be formed on the silicon oxide layer. The mask layer may be etched using a second pattern as an etching mask to form a mask pattern, and the second pattern may includes the first pattern, the silicon oxide layer and the coating pattern. The mask pattern may have a uniform size.

The present disclosure relates a method of manufacturing an integrated chip structure. The method forms an intermediate first material layer over a substrate and an intermediate second material layer on the intermediate first material layer. The intermediate second material layer is patterned to form an insulating layer. The intermediate first material layer is patterned to form a first material layer having an outermost sidewall indented inward from an outermost sidewall of the insulating layer. An ion bombardment process is performed on the insulating layer to dislodge one or more atoms from the insulating layer. A re-deposition process is performed to re-deposit the one or more atoms onto the outermost sidewall of the first material layer and to form a self-filling spacer below the insulating layer.

The present disclosure relates a method of manufacturing an integrated chip structure. The method forms an intermediate first material layer over a substrate and an intermediate second material layer on the intermediate first material layer. The intermediate second material layer is patterned to form an insulating layer. The intermediate first material layer is patterned to form a first material layer having an outermost sidewall indented inward from an outermost sidewall of the insulating layer. An ion bombardment process is performed on the insulating layer to dislodge one or more atoms from the insulating layer. A re-deposition process is performed to re-deposit the one or more atoms onto the outermost sidewall of the first material layer and to form a self-filling spacer below the insulating layer.