A manufacturing method of a thin film transistor substrate and the thin film transistor substrate manufactured by using the manufacturing method are provided. The manufacturing method includes: providing a substrate layer, forming a gate electrode layer on the substrate layer, forming an insulating layer on the substrate layer and the gate electrode layer by using a first solution, forming a channel layer on the insulating layer by using a second solution, and forming a source/drain electrode layer on the insulating layer. The insulating layer and the channel layer are formed by processes using solution, so high vacuum equipment is not required, and production costs are reduced.

The present invention provides a preparation method for a fully-transparent thin film transistor, wherein a transparent conductive gate electrode layer of the fully-transparent thin film transistor is used as a photolithographic mask, a photoresist is exposed through a rear surface of a transparent substrate, the transparent substrate has a transmittance higher than 60% to an exposure light beam, and the transparent conductive gate electrode layer has a transmittance lower than 5% to the exposure light beam. In the preparation method for a fully-transparent thin film transistor provided by the present invention, by using a self-aligned technology, the process complexity and the feature size of the device can both be reduced.

The present invention provides a preparation method for a fully-transparent thin film transistor, wherein a transparent conductive gate electrode layer of the fully-transparent thin film transistor is used as a photolithographic mask, a photoresist is exposed through a rear surface of a transparent substrate, the transparent substrate has a transmittance higher than 60% to an exposure light beam, and the transparent conductive gate electrode layer has a transmittance lower than 5% to the exposure light beam. In the preparation method for a fully-transparent thin film transistor provided by the present invention, by using a self-aligned technology, the process complexity and the feature size of the device can both be reduced.

According to one embodiment, a substrate processing apparatus includes a table configured to place a substrate thereon and to connect the substrate to a positive electrode, an counter electrode located opposite to the table, having a plurality of holes, and connected to a negative electrode, and a holding unit located opposite to the table across the counter electrode and configured to supply a chemical liquid to the counter electrode while holding the counter electrode.

According to one embodiment, a substrate processing apparatus includes a table configured to place a substrate thereon and to connect the substrate to a positive electrode, an counter electrode located opposite to the table, having a plurality of holes, and connected to a negative electrode, and a holding unit located opposite to the table across the counter electrode and configured to supply a chemical liquid to the counter electrode while holding the counter electrode.

A semiconductor device includes an extremely thin semiconductor-on-insulator substrate (ETSOI) having a base substrate, a thin semiconductor layer and a buried dielectric therebetween. A device channel is formed in the thin semiconductor layer. Source and drain regions are formed at opposing positions relative to the device channel. The source and drain regions include an n-type material deposited on the buried dielectric within a thickness of the thin semiconductor layer. A gate structure is formed over the device channel.

A semiconductor device includes an extremely thin semiconductor-on-insulator substrate (ETSOI) having a base substrate, a thin semiconductor layer and a buried dielectric therebetween. A device channel is formed in the thin semiconductor layer. Source and drain regions are formed at opposing positions relative to the device channel. The source and drain regions include an n-type material deposited on the buried dielectric within a thickness of the thin semiconductor layer. A gate structure is formed over the device channel.

A manufacturing method of a thin film transistor substrate and the thin film transistor substrate manufactured by using the manufacturing method are provided. The manufacturing method includes: providing a substrate layer, forming a gate electrode layer on the substrate layer, forming an insulating layer on the substrate layer and the gate electrode layer by using a first solution, forming a channel layer on the insulating layer by using a second solution, and forming a source/drain electrode layer on the insulating layer. The insulating layer and the channel layer are formed by processes using solution, so high vacuum equipment is not required, and production costs are reduced.

A system and method comprising depositing a first layer on a substrate, in which the first layer comprises at least one of, a metal oxide and carbon based derivative, wherein the first layer is a gate electrode of a tag. Depositing a second layer, annealing said second layer, and treating a surface of the second layer, wherein the surface treatment is configured to enhance conductivity. Depositing a third layer, wherein the third layer is a gate dielectric of the tag. Depositing a fourth and a fifth layer. The fifth layer comprises at least an Indium Gallium Zinc Oxide layer and as a semiconductor layer of the tag. Photonic curing the fifth layer. Depositing a sixth and a seventh layer, in which the sixth layer is a source contact layer and said seventh layer is a drain contact layer of the tag.

A system and method comprising depositing a first layer on a substrate, in which the first layer comprises at least one of, a metal oxide and carbon based derivative, wherein the first layer is a gate electrode of a tag. Depositing a second layer, annealing said second layer, and treating a surface of the second layer, wherein the surface treatment is configured to enhance conductivity. Depositing a third layer, wherein the third layer is a gate dielectric of the tag. Depositing a fourth and a fifth layer. The fifth layer comprises at least an Indium Gallium Zinc Oxide layer and as a semiconductor layer of the tag. Photonic curing the fifth layer. Depositing a sixth and a seventh layer, in which the sixth layer is a source contact layer and said seventh layer is a drain contact layer of the tag.