To provide an electroconductive thin film, containing: a metal oxide containing indium and tin; and gold.

To provide an electroconductive thin film, containing: a metal oxide containing indium and tin; and gold.

An object is to provide a novel method in place of the above-described conventional technology, as a technique for obtaining a thin film with a wiring pattern applied. A method for manufacturing a wiring pattern according to the present invention is characterized in that the method includes: a laminate forming step of forming a laminate by bringing a first member that has a resist layer and a metal layer formed on the resist layer into contact with a second member that includes a substrate; a resist layer patterning step of subjecting the resist layer to patterning; and an etching step of selectively removing the metal layer.

Disclosed are curable linear polymers that can be used as active and/or passive organic materials in various electronic, optical, and optoelectronic devices. In some embodiments, the device can include an organic semiconductor layer and a dielectric layer prepared from such curable linear polymers. In some embodiments, the device can include a passivation layer prepared from the linear polymers described herein. The present linear polymers can be solution-processed, then cured thermally (particularly, at relatively low temperatures) and/or photochemically into various thin film materials with desirable properties.

Disclosed are curable linear polymers that can be used as active and/or passive organic materials in various electronic, optical, and optoelectronic devices. In some embodiments, the device can include an organic semiconductor layer and a dielectric layer prepared from such curable linear polymers. In some embodiments, the device can include a passivation layer prepared from the linear polymers described herein. The present linear polymers can be solution-processed, then cured thermally (particularly, at relatively low temperatures) and/or photochemically into various thin film materials with desirable properties.

Disclosed are an electronic device and a method of fabricating the same. The method of fabricating an electronic device comprises providing on a substrate a channel layer including a two-dimensional material, providing a metal fiber layer on a first surface of a conductive layer, providing the metal fiber layer on the channel layer, and performing a thermal treatment process to form a junction layer where a portion of the metal fiber layer is covalently bonded to a portion of the channel layer.

Disclosed are an electronic device and a method of fabricating the same. The method of fabricating an electronic device comprises providing on a substrate a channel layer including a two-dimensional material, providing a metal fiber layer on a first surface of a conductive layer, providing the metal fiber layer on the channel layer, and performing a thermal treatment process to form a junction layer where a portion of the metal fiber layer is covalently bonded to a portion of the channel layer.

A semiconductor device includes an extremely thin semiconductor-on-insulator substrate (ETSOI) having a base substrate, a thin semiconductor layer and a buried dielectric therebetween. A device channel is formed in the thin semiconductor layer. Source and drain regions are formed at opposing positions relative to the device channel. The source and drain regions include an n-type material deposited on the buried dielectric within a thickness of the thin semiconductor layer. A gate structure is formed over the device channel.

A semiconductor device includes an extremely thin semiconductor-on-insulator substrate (ETSOI) having a base substrate, a thin semiconductor layer and a buried dielectric therebetween. A device channel is formed in the thin semiconductor layer. Source and drain regions are formed at opposing positions relative to the device channel. The source and drain regions include an n-type material deposited on the buried dielectric within a thickness of the thin semiconductor layer. A gate structure is formed over the device channel.

A plating method includes forming a catalyst layer 118 on a surface of a substrate including an inner surface of a recess 112; drying the substrate having the catalyst layer formed thereon such that an inside of the recess is dried as well; removing the catalyst layer at least on the surface of the substrate at the outside of the recess by supplying a processing liquid, which is configured to dissolve a material of the surface of the substrate, onto the surface of the substrate while rotating the dried substrate and while preventing or suppressing the processing liquid from being introduced into the dried inside of the recess; and forming a plating layer 119 on the inside of the recess, at which the catalyst layer is not removed, by an electroless plating process.