An element chip manufacturing method including: a preparing step of preparing a substrate including a plurality of element regions and a dicing region defining the element regions, the substrate having a first surface and a second surface opposite the first surface; a laser scribing step of applying a laser beam to the dicing region from a side of the first surface, to form a groove corresponding to the dicing region and being shallower than a thickness of the substrate; a cleaning step of exposing the first surface of the substrate to a first plasma, to remove debris on the groove; and a dicing step of exposing the substrate at a bottom of the groove to a second plasma after the cleaning step, to dice the substrate into element chips including the element regions. The first plasma is generated from a process gas containing a carbon oxide gas.

A package includes a semiconductor carrier, a first die, a second die, a first encapsulant, a second encapsulant, a first through insulating via (TIV), and a second TIV. The semiconductor carrier has a contact via embedded therein. The contact via is electrically grounded. The first die is disposed over the semiconductor carrier. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The second encapsulant laterally encapsulates the second die. The first TIV is aside the first die. The first TIV penetrates through the first encapsulant and is electrically connected to the contact via. The second TIV is aside the second die. The second TIV penetrates through the second encapsulant and is electrically connected to the contact via and the first TIV.

A package includes a semiconductor carrier, a first die, a second die, a first encapsulant, a second encapsulant, a first through insulating via (TIV), and a second TIV. The semiconductor carrier has a contact via embedded therein. The contact via is electrically grounded. The first die is disposed over the semiconductor carrier. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The second encapsulant laterally encapsulates the second die. The first TIV is aside the first die. The first TIV penetrates through the first encapsulant and is electrically connected to the contact via. The second TIV is aside the second die. The second TIV penetrates through the second encapsulant and is electrically connected to the contact via and the first TIV.

A method for thinning a semiconductor die includes providing the semiconductor die having electrical contacts electrically connected to and protruding from a top surface of the semiconductor die. The electrical contacts are spaced from one another on the top surface of the semiconductor die. The electrical contacts are encapsulated and a portion of the top surface of the semiconductor die is covered by a semisolid filler. The semisolid filler fills the space between the electrical contacts. An adhesive layer is applied to a top surface of the semisolid filler, and a backgrinding process is performed on a bottom surface of the semiconductor die. The method allows for thin semiconductor dies to be manufactured while reducing the risk of manufacturing defects associated with backgrinding.

A method for thinning a semiconductor die includes providing the semiconductor die having electrical contacts electrically connected to and protruding from a top surface of the semiconductor die. The electrical contacts are spaced from one another on the top surface of the semiconductor die. The electrical contacts are encapsulated and a portion of the top surface of the semiconductor die is covered by a semisolid filler. The semisolid filler fills the space between the electrical contacts. An adhesive layer is applied to a top surface of the semisolid filler, and a backgrinding process is performed on a bottom surface of the semiconductor die. The method allows for thin semiconductor dies to be manufactured while reducing the risk of manufacturing defects associated with backgrinding.

First to third insulators are successively formed in this order over a first conductor over a semiconductor substrate; a hard mask with a first opening is formed thereover; a resist mask with a second opening is formed thereover; a third opening is formed in the third insulator; a fourth opening is formed in the second insulator; the resist mask is removed; a fifth opening is formed in the first to third insulators; a second conductor is formed to cover an inner wall and a bottom surface of the fifth opening; a third conductor is formed thereover; polishing treatment is performed so that the hard mask is removed, and that levels of top surfaces of the second and third conductors and the third insulator are substantially equal to each other; and an oxide semiconductor is formed thereover. The second insulator is less permeable to hydrogen than the first and third insulators, the second conductor is less permeable to hydrogen than the third conductor.

First to third insulators are successively formed in this order over a first conductor over a semiconductor substrate; a hard mask with a first opening is formed thereover; a resist mask with a second opening is formed thereover; a third opening is formed in the third insulator; a fourth opening is formed in the second insulator; the resist mask is removed; a fifth opening is formed in the first to third insulators; a second conductor is formed to cover an inner wall and a bottom surface of the fifth opening; a third conductor is formed thereover; polishing treatment is performed so that the hard mask is removed, and that levels of top surfaces of the second and third conductors and the third insulator are substantially equal to each other; and an oxide semiconductor is formed thereover. The second insulator is less permeable to hydrogen than the first and third insulators, the second conductor is less permeable to hydrogen than the third conductor.

A package includes a semiconductor carrier, a first die, a second die, a redistribution structure, and an electron transmission path. The first die is disposed over the semiconductor carrier. The second die is stacked on the first die. The redistribution structure is over the second die. The electron transmission path extends from the semiconductor carrier to the redistribution structure. The electron transmission path is electrically connected to a ground voltage. A first portion of the electron transmission path is embedded in the semiconductor carrier, a second portion of the electron transmission path is aside the first die, and a third portion of the electron transmission path is aside the second die.

A package includes a semiconductor carrier, a first die, a second die, a redistribution structure, and an electron transmission path. The first die is disposed over the semiconductor carrier. The second die is stacked on the first die. The redistribution structure is over the second die. The electron transmission path extends from the semiconductor carrier to the redistribution structure. The electron transmission path is electrically connected to a ground voltage. A first portion of the electron transmission path is embedded in the semiconductor carrier, a second portion of the electron transmission path is aside the first die, and a third portion of the electron transmission path is aside the second die.

A semiconductor manufacturing apparatus is a semiconductor manufacturing apparatus for holding a polishing object on a polishing head and polishing a surface of the polishing object. The semiconductor manufacturing apparatus includes a plurality of laser irradiation parts on the polishing head. At least one of the laser irradiation parts is a laser irradiation part configured to radiate a laser beam toward the back surface side of the polishing object.