A semiconductor device with low parasitic capacitance is provided. The semiconductor device includes a first oxide insulator, an oxide semiconductor, a second oxide insulator, a gate insulating layer, a gate electrode layer, source and drain electrode layers and an insulating layer. The oxide semiconductor includes first to fifth regions. The first region overlaps with the source electrode layer. The second region overlaps with the drain electrode layer. The third region overlaps with the gate electrode layer. The fourth region is between the first region and the third region. The fifth region is between the second region and the third region. The fourth region and the fifth region each contain an element N (N is hydrogen, nitrogen, helium, neon, argon, krypton, or xenon). A top surface of the insulating layer is positioned at a lower level than top surfaces of the source and drain electrode layers.

A semiconductor device with low parasitic capacitance is provided. The semiconductor device includes a first oxide insulator, an oxide semiconductor, a second oxide insulator, a gate insulating layer, a gate electrode layer, source and drain electrode layers and an insulating layer. The oxide semiconductor includes first to fifth regions. The first region overlaps with the source electrode layer. The second region overlaps with the drain electrode layer. The third region overlaps with the gate electrode layer. The fourth region is between the first region and the third region. The fifth region is between the second region and the third region. The fourth region and the fifth region each contain an element N (N is hydrogen, nitrogen, helium, neon, argon, krypton, or xenon). A top surface of the insulating layer is positioned at a lower level than top surfaces of the source and drain electrode layers.

A manufacturing method of a semiconductor structure includes the following operations. A stacked structure is formed on a substrate. The stacked structure includes semiconductor layers and sacrificial layers that are alternately stacked, in which the sacrificial layers include germanium, and germanium concentrations of the sacrificial layers decrease from bottom to top. A dummy gate structure is formed on the stacked structure. A spacer is formed on both sides of the dummy gate structure. The dummy gate structure is removed, thereby forming an opening. The sacrificial layers are removed from the opening. A gate structure is formed to cover the semiconductor layers. In another manufacturing method, the stacked structure includes semiconductor layers and sacrificial layers that are alternately stacked, in which thicknesses of the semiconductor layers increase from bottom to top, or thicknesses of the sacrificial layers increase from bottom to top.

A manufacturing method of a semiconductor structure includes the following operations. A stacked structure is formed on a substrate. The stacked structure includes semiconductor layers and sacrificial layers that are alternately stacked, in which the sacrificial layers include germanium, and germanium concentrations of the sacrificial layers decrease from bottom to top. A dummy gate structure is formed on the stacked structure. A spacer is formed on both sides of the dummy gate structure. The dummy gate structure is removed, thereby forming an opening. The sacrificial layers are removed from the opening. A gate structure is formed to cover the semiconductor layers. In another manufacturing method, the stacked structure includes semiconductor layers and sacrificial layers that are alternately stacked, in which thicknesses of the semiconductor layers increase from bottom to top, or thicknesses of the sacrificial layers increase from bottom to top.

Vapor deposition methods for depositing transition metal dichalcogenide (TMDC) films, such as rhenium sulfide thin films, are provided. In some embodiments TMDC thin films are deposited using a deposition cycle in which a substrate in a reaction space is alternately and sequentially contacted with a vapor phase transition metal precursor, such as a transition metal halide, a reactant comprising a reducing agent, such as NH.sub.3 and a chalcogenide precursor. In some embodiments rhenium sulfide thin films are deposited using a vapor phase rhenium halide precursor, a reducing agent and a sulfur precursor. The deposited TMDC films can be etched by chemical vapor etching using an oxidant such as O.sub.2 as the etching reactant and an inert gas such as N.sub.2 to remove excess etching reactant. The TMDC thin films may find use, for example, as 2D materials.

Vapor deposition methods for depositing transition metal dichalcogenide (TMDC) films, such as rhenium sulfide thin films, are provided. In some embodiments TMDC thin films are deposited using a deposition cycle in which a substrate in a reaction space is alternately and sequentially contacted with a vapor phase transition metal precursor, such as a transition metal halide, a reactant comprising a reducing agent, such as NH.sub.3 and a chalcogenide precursor. In some embodiments rhenium sulfide thin films are deposited using a vapor phase rhenium halide precursor, a reducing agent and a sulfur precursor. The deposited TMDC films can be etched by chemical vapor etching using an oxidant such as O.sub.2 as the etching reactant and an inert gas such as N.sub.2 to remove excess etching reactant. The TMDC thin films may find use, for example, as 2D materials.

The invention includes a method of promoting atomic layer etching (ALE) of a surface. In certain embodiments, the method comprises sequential reactions with a metal precursor and a halogen-containing gas. The invention provides a solid substrate obtained according to any of the methods of the invention. The invention further provides a porous substrate obtained according to any of the methods of the invention. The invention further provides a patterned solid substrate obtained according to any of the methods of the invention.

Tin oxide films are used as spacers and hardmasks in semiconductor device manufacturing. In one method, tin oxide layer (e.g., spacer footing) needs to be selectively etched in a presence of an exposed silicon-containing layer, such as SiOC, SiON, SiONC, amorphous silicon, SiC, or SiN. In order to reduce damage to the silicon-containing layer the process involves passivating the silicon-containing layer towards a tin oxide etch chemistry, etching the tin oxide, and repeating passivation and etch in an alternating fashion. For example, passivation and etch can be each performed between 2-50 times. In one implementation, passivation is performed by treating the substrate with an oxygen-containing reactant, activated in a plasma, and the tin oxide etching is performed by a chlorine-based chemistry, such as using a mixture of Cl.sub.2 and BCl.sub.3.

An etchant composition includes an inorganic acid compound of about 8 wt % to about 15 wt %, a sulfonic acid compound of about 2.5 wt % to about 8 wt %, a sulfate compound of about 6 wt % to about 14 wt %, an organic acid compound of about 40 wt % to about 55 wt %, a metal or metal salt of about 0.01 wt % to about 0.06 wt %, and water.

The reliability of a transistor including an oxide semiconductor can be improved by suppressing a change in electrical characteristics. A transistor included in a semiconductor device includes a first oxide semiconductor film over a first insulating film, a gate insulating film over the first oxide semiconductor film, a second oxide semiconductor film over the gate insulating film, and a second insulating film over the first oxide semiconductor film and the second oxide semiconductor film. The first oxide semiconductor film includes a channel region in contact with the gate insulating film, a source region in contact with the second insulating film, and a drain region in contact with the second insulating film. The second oxide semiconductor film has a higher carrier density than the first oxide semiconductor film.