Patent classifications
H01L21/465
Method of manufacturing semiconductor device, substrate processing method and substrate processing apparatus
Provided are: forming an oxycarbonitride film, an oxycarbide film or an oxide film on a substrate by alternately performing a specific number of times: forming a first layer containing the specific element, nitrogen and carbon, on the substrate, by alternately performing a specific number of times, supplying a first source containing the specific element and a halogen-group to the substrate in a processing chamber, and supplying a second source containing the specific element and an amino-group to the substrate in the processing chamber; and forming a second layer by oxidizing the first layer by supplying an oxygen-containing gas, and an oxygen-containing gas and a hydrogen-containing gas to the substrate in the processing chamber.
Semiconductor device and method for manufacturing same
A semiconductor device includes a thin film transistor, wherein: a semiconductor layer of the thin film transistor has a layered structure including a lower oxide semiconductor layer including In, Ga, Zn and Sn and an upper oxide semiconductor layer arranged on the lower oxide semiconductor layer and including In, Ga and Zn; a thickness of the lower oxide semiconductor layer is 20 nm or less; an atomic ratio of Sn with respect to all metal elements of the lower oxide semiconductor layer is 5% or more; the upper oxide semiconductor layer includes no Sn, or an atomic ratio of Sn with respect to all metal elements of the upper oxide semiconductor layer is smaller than an atomic ratio of Sn with respect to all metal elements of the lower oxide semiconductor layer; and a first angle θ1 between a side surface and a lower surface of the lower oxide semiconductor layer is smaller than a second angle θ2 between a side surface and a lower surface of the upper oxide semiconductor layer.
SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, AND ELECTRONIC DEVICE
A semiconductor device with reduced parasitic capacitance is provided. A stack is formed on an insulating layer, the stack comprising a first oxide insulating layer, an oxide semiconductor layer over the first oxide insulating layer, and a second oxide insulating layer on the oxide semiconductor layer; a gate electrode layer and a gate insulating layer are formed on the second oxide insulating layer; a first low-resistance region is formed by adding a first ion to the second oxide semiconductor layer using the gate electrode layer as a mask; a sidewall insulating layer is formed on an outer side of the gate electrode layer; a second conductive layer is formed over the gate electrode layer, the sidewall insulating layer, and the second insulating layer; and an alloyed region in the second oxide semiconductor layer is formed by performing heat treatment.
SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, AND ELECTRONIC DEVICE
A semiconductor device with reduced parasitic capacitance is provided. A stack is formed on an insulating layer, the stack comprising a first oxide insulating layer, an oxide semiconductor layer over the first oxide insulating layer, and a second oxide insulating layer on the oxide semiconductor layer; a gate electrode layer and a gate insulating layer are formed on the second oxide insulating layer; a first low-resistance region is formed by adding a first ion to the second oxide semiconductor layer using the gate electrode layer as a mask; a sidewall insulating layer is formed on an outer side of the gate electrode layer; a second conductive layer is formed over the gate electrode layer, the sidewall insulating layer, and the second insulating layer; and an alloyed region in the second oxide semiconductor layer is formed by performing heat treatment.
ATOMIC LAYER DEPOSITION AND ETCHING OF TRANSITION METAL DICHALCOGENIDE THIN FILMS
Vapor deposition methods for depositing transition metal dichalcogenide (TMDC) films, such as rhenium sulfide thin films, are provided. In some embodiments TMDC thin films are deposited using a deposition cycle in which a substrate in a reaction space is alternately and sequentially contacted with a vapor phase transition metal precursor, such as a transition metal halide, a reactant comprising a reducing agent, such as NH.sub.3 and a chalcogenide precursor. In some embodiments rhenium sulfide thin films are deposited using a vapor phase rhenium halide precursor, a reducing agent and a sulfur precursor. The deposited TMDC films can be etched by chemical vapor etching using an oxidant such as O.sub.2 as the etching reactant and an inert gas such as N.sub.2 to remove excess etching reactant. The TMDC thin films may find use, for example, as 2D materials.
ATOMIC LAYER DEPOSITION AND ETCHING OF TRANSITION METAL DICHALCOGENIDE THIN FILMS
Vapor deposition methods for depositing transition metal dichalcogenide (TMDC) films, such as rhenium sulfide thin films, are provided. In some embodiments TMDC thin films are deposited using a deposition cycle in which a substrate in a reaction space is alternately and sequentially contacted with a vapor phase transition metal precursor, such as a transition metal halide, a reactant comprising a reducing agent, such as NH.sub.3 and a chalcogenide precursor. In some embodiments rhenium sulfide thin films are deposited using a vapor phase rhenium halide precursor, a reducing agent and a sulfur precursor. The deposited TMDC films can be etched by chemical vapor etching using an oxidant such as O.sub.2 as the etching reactant and an inert gas such as N.sub.2 to remove excess etching reactant. The TMDC thin films may find use, for example, as 2D materials.
MICRON SCALE TIN OXIDE-BASED SEMICONDUCTOR DEVICES
Micron scale tin oxide-based semiconductor devices are provided. Reactive-ion etching is used to produce a micron-scale electronic device using semiconductor films with tin oxides, such as barium stannate (BaSnO3). The electronic devices produced with this approach have high mobility, drain current, and on-off ratio without adversely affecting qualities of the tin oxide semiconductor, such as resistivity, electron or hole mobility, and surface roughness. In this manner, electronic devices, such as field-effect transistors (e.g., thin-film transistors (TFTs)), are produced having micron scale channel lengths and exhibiting complete depletion at room temperature.
ALTERNATING ETCH AND PASSIVATION PROCESS
Tin oxide films are used as spacers and hardmasks in semiconductor device manufacturing. In one method, tin oxide layer (e.g., spacer footing) needs to be selectively etched in a presence of an exposed silicon-containing layer, such as SiOC, SiON, SiONC, amorphous silicon, SiC, or SiN. In order to reduce damage to the silicon-containing layer the process involves passivating the silicon-containing layer towards a tin oxide etch chemistry, etching the tin oxide, and repeating passivation and etch in an alternating fashion. For example, passivation and etch can be each performed between 2-50 times. In one implementation, passivation is performed by treating the substrate with an oxygen-containing reactant, activated in a plasma, and the tin oxide etching is performed by a chlorine-based chemistry, such as using a mixture of Cl.sub.2 and BCl.sub.3
METHOD OF MANUFACTURING A PHOTOVOLTAIC CELL
Method of manufacturing a photovoltaic cell, comprising the steps of: providing a photovoltaic conversion device; providing a transparent conductive oxide layer upon at least a first face of said photovoltaic conversion device; forming a self-assembled monolayer on said transparent conductive oxide layer, said self-assembled monolayer being based on molecules terminated by at least one group F which is chosen from: a phosphonic acid group, a P(O)O.sub.2.sup.−M.sup.+ group, a OPO.sub.3H.sub.2 group, or an OP(O)O.sub.2.sup.−M.sup.+ group, wherein M.sup.+ is a metal cation; patterning said self-assembled monolayer so as to define at least one plateable zone in which said transparent conductive oxide layer is exposed; plating a metal onto said at least one plateable zone.
Diode
A diode includes an n-type semiconductor layer including an n-type Ga.sub.2O.sub.3-based single crystal, and a p-type semiconductor layer including a p-type semiconductor in which a volume of an amorphous portion is higher than a volume of a crystalline portion. The n-type semiconductor layer and the p-type semiconductor layer form a pn junction.