A manufacturing method of an array substrate, including: forming a pattern layer including a pixel electrode, and a pattern layer including a gate electrode and a gate line on a base substrate; on the substrate with the pattern layer including the gate electrode and the gate line formed thereon, forming a gate insulating layer, a pattern layer at least including a metal oxide semiconductor active layer and a pattern layer at least including an etch stop layer; wherein, a first via hole for exposing the pixel electrode is formed over the pixel electrode; on the substrate with the etch stop layer formed thereon, forming a pattern layer including a source electrode, a drain electrode and a data line; wherein, the source electrode and the drain electrode each contact a metal oxide semiconductor active layer, and the drain electrode is electrically connected to the pixel electrode through the first via hole.

A semiconductor structure includes a first dielectric layer, a first conductive via, a second conductive via and an etch stop layer. The first conductive via and the second conductive via are respectively disposed in the first dielectric layer. The etch stop layer is disposed on the first dielectric layer and contacts the first and second conductive vias. The etch stop layer includes nitrogen-and-oxygen-doped silicon carbide (NODC).

A method of manufacturing a linear grid on a substrate to form a linear grid pattern of a display panel, the method including: laminating a negative photoresist layer having a linear grid pattern on a first area of a substrate, said substrate including a pattern forming layer disposed thereon; laminating a positive photoresist layer having a linear grid pattern on a second area of the substrate and overlapping at least a portion of the negative photoresist layer of the first area; covering the second area with a mask and exposing the first area; and forming a linear grid pattern by removing the mask and etching the pattern forming layer.

The present disclosure relates to the technical field of semiconductor technologies and discloses a semiconductor device and a manufacturing method therefor. The method includes forming a growth substrate by providing a substrate structure containing a sacrificial substrate, a first dielectric layer on the sacrificial substrate, and a plurality of recesses formed through the first dielectric layer and into the sacrificial substrate, by forming a buffer layer covering exposes surfaces of the plurality of recesses, by selectively growing a graphene layer on the buffer layer, and by filling the plurality of recesses with a second dielectric layer. The method further includes attaching the growth substrate to a bonding substrate such that the second dielectric layer attaches to the bonding substrate; removing the sacrificial substrate; and removing the buffer layer so as to expose the graphene layer. The method of present disclosure avoids adverse effects from patterning graphene by using selective growth of graphene on a patterned buffer layer.

A thin film transistor array panel including: a substrate; a semiconductor layer disposed on the substrate; a source electrode and a drain electrode overlapping the semiconductor layer, and a gate electrode overlapping the semiconductor layer; and a first ohmic contact disposed between the semiconductor layer and the source electrode and a second ohmic contact disposed between the semiconductor layer and the drain electrode. The semiconductor layer includes a channel part that does not overlap the source electrode and the drain electrode. The first ohmic contact includes a first edge and the second ohmic contact includes a second edge. The first and second edges face each other across the channel part of the semiconductor layer. The first edge of the first ohmic contact is protruded from the source electrode toward the channel part and the second edge of the second ohmic contact is protruded from the drain electrode toward the channel part.

A thin film transistor array panel including: a substrate; a semiconductor layer disposed on the substrate; a source electrode and a drain electrode overlapping the semiconductor layer, and a gate electrode overlapping the semiconductor layer; and a first ohmic contact disposed between the semiconductor layer and the source electrode and a second ohmic contact disposed between the semiconductor layer and the drain electrode. The semiconductor layer includes a channel part that does not overlap the source electrode and the drain electrode. The first ohmic contact includes a first edge and the second ohmic contact includes a second edge. The first and second edges face each other across the channel part of the semiconductor layer. The first edge of the first ohmic contact is protruded from the source electrode toward the channel part and the second edge of the second ohmic contact is protruded from the drain electrode toward the channel part.

A plasma processing method of forming a protective film for suppressing etching only a desired material in a pattern to etch a pattern is provided. A plasma processing method for plasma etching a film to be etched formed on a sample includes a cleaning step of cleaning a surface of the sample, a protective film forming step of selectively forming a protective film on a desired material in a pattern formed on the film to be etched, an oxidation step of oxidizing the protective film after the protective film forming step, and an etching step of plasma-etching the film to be etched.

Provided is a technology including a nozzle base end portion which is provided in a processing chamber processing a substrate to extend in a vertical direction and into which a processing gas processing the substrate is introduced, a nozzle distal end portion which is configured in a U shape and in which a gas supply hole supplying the processing gas is provided to a side surface of the substrate, and a gas residence suppressing hole which is provided in a downstream end of the nozzle distal end portion and has a diameter larger than that of the gas supply hole.

An optical device includes a gallium and nitrogen containing substrate comprising a surface region configured in a (20-2-1) orientation, a (30-3-1) orientation, or a (30-31) orientation, within +/10 degrees toward c-plane and/or a-plane from the orientation. Optical devices having quantum well regions overly the surface region are also disclosed.

Methods of depositing a film on a substrate surface include surface mediated reactions in which a film is grown over one or more cycles of reactant adsorption and reaction. In one aspect, the method is characterized by intermittent delivery of dopant species to the film between the cycles of adsorption and reaction.