FinFET structures and methods of forming the same are disclosed. In a method, a recess is formed exposing a plurality of semiconductor fins on a wafer. A dummy contact material is formed in the recess. The dummy contact material contains carbon. The dummy contact material is cured with one or more baking steps. The one or more baking steps harden the dummy contact material. A first portion of the dummy contact material is replaced with an inter-layer dielectric. A second portion of the dummy contact material is replaced with a plurality of contacts. The plurality of contacts are electrically coupled to source/drain regions of the plurality of semiconductor fins.

The present disclosure relates to an integrated circuit (IC) that includes a HKMG hybrid non-volatile memory (NVM) device and that provides small scale and high performance, and a method of formation. In some embodiments, the integrated circuit includes a memory region having a NVM device with a pair of control gate electrodes separated from a substrate by corresponding floating gates. A pair of select gate electrodes are disposed at opposite sides of the pair of control gate electrodes comprise polysilicon. A logic region is disposed adjacent to the memory region and has a logic device with a metal gate electrode disposed over a logic gate dielectric and having bottom and sidewall surfaces covered by a high-k gate dielectric layer.

A method for manufacturing a resistive device, includes depositing a first electrically conductive layer on a substrate; forming an etching mask on the first conductive layer; etching the first conductive layer through the mask, such as to obtain a plurality of electrically conductive pillars separated from one another; and forming storage elements with variable electrical resistance at the tops of the electrically conductive pillars, such that each storage element is supported by one of the electrically conductive pillars, the step of forming the storage elements including the following operations depositing a first layer by non-collimated cathode sputtering at normal incidence relative to the substrate; and depositing a second layer on the first layer by cathode sputtering, the second layer including a first chemical species sputtered at an oblique incidence.

A method for manufacturing a resistive device, includes depositing a first electrically conductive layer on a substrate; forming an etching mask on the first conductive layer; etching the first conductive layer through the mask, such as to obtain a plurality of electrically conductive pillars separated from one another; and forming storage elements with variable electrical resistance at the tops of the electrically conductive pillars, such that each storage element is supported by one of the electrically conductive pillars, the step of forming the storage elements including the following operations depositing a first layer by non-collimated cathode sputtering at normal incidence relative to the substrate; and depositing a second layer on the first layer by cathode sputtering, the second layer including a first chemical species sputtered at an oblique incidence.

MMIC circuits with thin film transistors are provided without the need of grinding and etching of the substrate after the fabrication of active and passive components. Furthermore, technology for active devices based on non-toxic compound semiconductors is provided. The success in the MMIC methods and structures without substrate grinding/etching and the use of semiconductors without toxic elements for active components will reduce manufacturing time, decrease economic cost and environmental burden. MMIC structures are provided where the requirements for die or chip attachment, alignment and wire bonding are eliminated completely or minimized. This will increase the reproducibility and reduce the manufacturing time for the MMIC circuits and modules.

A semiconductor device includes a first semiconductor channel, a second semiconductor channel, a first gate stack and a second gate stack. The first gate stack is present on the first semiconductor channel. The first gate stack includes a first work function layer and a first interposing layer present between the first semiconductor channel and the first work function layer. The second gate stack is present on the second semiconductor channel. The second gate stack includes a second work function layer and a second interposing layer present between the second semiconductor channel and the second work function layer. The first interposing layer and the second interposing layer are different at least in tantalum nitride amount.

To provide a method by which a semiconductor device including a thin film transistor with excellent electric characteristics and high reliability is manufactured with a small number of steps. After a channel protective layer is formed over an oxide semiconductor film containing In, Ga, and Zn, a film having n-type conductivity and a conductive film are formed, and a resist mask is formed over the conductive film. The conductive film, the film having n-type conductivity, and the oxide semiconductor film containing In, Ga, and Zn are etched using the channel protective layer and gate insulating films as etching stoppers with the resist mask, so that source and drain electrode layers, a buffer layer, and a semiconductor layer are formed.

To provide a method by which a semiconductor device including a thin film transistor with excellent electric characteristics and high reliability is manufactured with a small number of steps. After a channel protective layer is formed over an oxide semiconductor film containing In, Ga, and Zn, a film having n-type conductivity and a conductive film are formed, and a resist mask is formed over the conductive film. The conductive film, the film having n-type conductivity, and the oxide semiconductor film containing In, Ga, and Zn are etched using the channel protective layer and gate insulating films as etching stoppers with the resist mask, so that source and drain electrode layers, a buffer layer, and a semiconductor layer are formed.

A package substrate, comprising a package comprising a substrate, the substrate comprising a dielectric layer, a via extending to a top surface of the dielectric layer; and a bond pad stack having a central axis and extending laterally from the via over the first layer. The bond pad stack is structurally integral with the via, wherein the bond pad stack comprises a first layer comprising a first metal disposed on the top of the via and extends laterally from the top of the via over the top surface of the dielectric layer adjacent to the via. The first layer is bonded to the top of the via and the dielectric layer, and a second layer is disposed over the first layer. A third layer is disposed over the second layer. The second layer comprises a second metal and the third layer comprises a third metal. The second layer and the third layer are electrically coupled to the via.

A method of fabricating a memory device includes forming an etching object layer and a lower sacrificial layer on a substrate, and forming an upper sacrificial pattern structure on the lower sacrificial layer. The upper sacrificial pattern structure includes a pad portion and a line portion on the lower sacrificial layer. An upper spacer is formed by covering a side wall of the upper sacrificial pattern structure. A lower sacrificial pattern structure including a lower sacrificial pad portion and a lower sacrificial line portion is formed by etching the lower sacrificial layer, by using the upper sacrificial pad portion and the upper spacer as a mask. A lower spacer layer is formed by covering the lower sacrificial pattern structure. A lower mask pattern including at least one line mask, bridge mask, and pad mask, is formed by etching the lower spacer layer and the lower sacrificial pattern structure.