A method includes performing an anneal on a wafer. The wafer includes a wafer-edge region, and an inner region encircled by the wafer-edge region. During the anneal, a first power applied on a portion of the wafer-edge region is at least lower than a second power for annealing the inner region.

A method of forming a conductive material on a semiconductor device. The method comprises removing at least a portion of a conductive pad within an aperture in a dielectric material over a substrate. The method further comprises forming a seed material at least within a bottom of the aperture and over the dielectric material, forming a protective material over the seed material within the aperture, and forming a conductive pillar in contact with the seed material through an opening in the protective material over surfaces of the seed material within the aperture. A method of forming an electrical connection between adjacent semiconductor devices, and a semiconductor device, are also described.

A display device and a method for fabricating the same are provided. The display device comprises pixels connected to scan lines, and to data lines crossing the scan lines, each of the pixels including a light emitting element, and a first transistor configured to control a driving current supplied to the light emitting element according to a data voltage applied from the data line, the first transistor including a first active layer having an oxide semiconductor, and a first oxide layer on the first active layer and having a crystalline oxide containing tin (Sn).

Formation methods of a semiconductor device structure are provided. The method includes providing a substrate having a low topography region and a high low topography region. The method also includes forming a first dielectric layer over the substrate. The method further includes forming a second dielectric layer over the stop layer. In addition, the method includes forming an opening in the first dielectric layer, the stop layer and the second dielectric layer. The method also includes forming a conductive material layer over the second dielectric layer. The conductive material layer fills the opening. The method further includes performing a polishing process over the conductive material layer until a top surface of the stop layer is exposed.

Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a conductive line feature over a substrate, a conductive etch stop layer over the conductive line feature, a contact via over the conductive etch stop layer, and a barrier layer disposed along a sidewall of the conductive line feature, a sidewall of the conductive etch stop layer, and a sidewall of the contact via.

A process of making a semiconductor structure. The process includes forming a wiring line; forming a reliability enhancement material on the wiring line; forming an interlayer dielectric (ILD) layer on the wiring line; forming a via opening through the ILD layer and reliability enhancement material to expose a surface of the wiring line; and filling the via opening with a metal to form a metal-filled via in contact with the wiring line wherein the reliability enhancement material is in direct contact with the metal-filled via; wherein the reliability enhancement material causes a compressive stress on the metal-filled via where it contacts the wiring line. Another embodiment includes the metal-filled via being an iso-via so that there is only one metal-filled via per wiring line.

A method for forming a semiconductor device includes forming a device structure having a floating gate, control gate, sidewall spacers, and source and drain regions. The device structure includes contact-hole regions and non-contact-hole regions. The method also includes forming a photo resist layer overlying the contact hole regions in the device structure and exposing the non-contact-hole regions, and forming a protective layer overlying the sacrificial layer and the exposed non-contact-hole regions. Next, an interlayer dielectric layer overlying the protective layer, and CMP (chemical mechanical polishing) is used to remove the inter-layer dielectric layer and the protective layer from above the photo resist. The photo resist layer is then removed from the contact-hole regions to expose contact holes.

The inventive concepts provide methods for fabricating a semiconductor device and semiconductor devices fabricated by the same. According to the method, conductive lines having a fine pitch smaller than the minimum pitch realized by an exposure process may be formed using two or three photolithography processes and two spacer formation processes. In addition, node separation regions of the conductive lines may be easily formed without a misalignment problem.

A charge array wafer includes a plurality of electrical charge storage cells disposed in an array configuration. A programmable amount of charge in each of the electrical charge storage cells causes a predetermined electric field to extend from a charge storage layer, through a passivation layer and into the space above the passivation layer, and the predetermined electric field is operable to attract deposition material to the top surface of the passivation layer. The deposition material may be a gas, a liquid or a powder, having a minimum feature size ranging from tens of nanometers to around five microns. The array of electrical charge storage cells includes an uninterrupted two-dimensional array extending over greater than 100×100 electrical charge storage cells without a select gate and without a bit-line contact positioned between any of the electrical charge storage cells.

A charge array wafer includes a plurality of electrical charge storage cells disposed in an array configuration. A programmable amount of charge in each of the electrical charge storage cells causes a predetermined electric field to extend from a charge storage layer, through a passivation layer and into the space above the passivation layer, and the predetermined electric field is operable to attract deposition material to the top surface of the passivation layer. The deposition material may be a gas, a liquid or a powder, having a minimum feature size ranging from tens of nanometers to around five microns. The array of electrical charge storage cells includes an uninterrupted two-dimensional array extending over greater than 100×100 electrical charge storage cells without a select gate and without a bit-line contact positioned between any of the electrical charge storage cells.