A semiconductor die is arranged on a substrate and an encapsulation of laser direct structuring (LDS) material is molded onto the semiconductor die. A through mold via (TMV) extends through the encapsulation. This TMV includes a collar section that extends through a first portion of the encapsulation from an outer surface to an intermediate level of the encapsulation, and a frusto-conical section that extends from a bottom of the collar section through a second portion of the encapsulation. The collar section has a first cross-sectional area at the intermediate level. The first end of the frusto-conical section has a second cross-section area at the intermediate level. The second cross-sectional area is smaller than the first cross-sectional area. The TMV can have an aspect ratio which is not limited to 1:1.

A semiconductor device includes: a first semiconductor element; a second semiconductor element; a first insulating base member adhesively bonded to the first semiconductor element; a first wiring connected to a first electrode of the first semiconductor element, and disposed on the first insulating base member; a second insulating base member adhesively bonded to the second semiconductor element, a second wiring connected to a third electrode of the second semiconductor element, and disposed on the second insulating base member; a first wiring member connected to a second electrode of the first semiconductor element; a second wiring member electrically connected to the first wiring and a fourth electrode of the second semiconductor element; and a third wiring member connected to the second wiring. A current flows in a first direction in the first wiring member, and flows in a second direction opposite to the first direction in the third wiring member.

A semiconductor device includes a semiconductor chip, a connection element configured to mechanically and electrically couple the semiconductor device to a circuit board, wherein the connection element is electrically coupled to the semiconductor chip and arranged in a mounting plane of the semiconductor device, and the semiconductor chip is mounted on the connection element. The semiconductor device further includes an extension element mechanically coupled to the connection element and extending in a direction out of the mounting plane, wherein the extension element is configured for air cooling.

This disclosure relates to a method of forming a wafer level chip scale semiconductor package, the method comprising: providing a carrier having a cavity formed therein; forming electrical contacts at a base portion and sidewalls portions of the cavity; placing a semiconductor die in the base of the cavity; connecting bond pads of the semiconductor die to the electrical contacts; encapsulating the semiconductor die; and removing the carrier to expose the electrical contacts, such that the electrical contacts are arranged directly on the encapsulation material.

A bus bar for a power semiconductor module arrangement includes a first end, and a second end. The first end is configured to be arranged inside a housing of the power semiconductor module arrangement. The second end is configured to be arranged outside of the housing and to be electrically contacted by an external bus bar. The second end includes a structured area that includes a plurality of protrusions. A height of each of the protrusions is between 10 μm and 1000 μm.

A die includes a metal pad, a passivation layer over the metal pad, and a polymer layer over the passivation layer. A metal pillar is over and electrically coupled to the metal pad. A metal ring is coplanar with the metal pillar. The polymer layer includes a portion coplanar with the metal pillar and the metal ring.

A semiconductor package includes a lead frame having a die paddle and a plurality of leads including a gate lead spaced apart from the die paddle. The semiconductor package further includes a semiconductor die attached to the die paddle and having a plurality of pads including a gate pad, a plurality of electrical conductors connecting the pads to the leads, an encapsulant encasing the semiconductor die and a portion of the leads such that part of the leads are not covered by the encapsulant, and a ferrite material embedded in the encapsulant and surrounding a portion of the electrical conductor that connects the gate pad to the gate lead. A method of manufacturing the semiconductor package and a semiconductor module with integrated ferrite material are also provided.

The present disclosure discloses a trench Insulated Gate Bipolar Transistor (IGBT) packaging structure and a method for manufacturing the trench Insulated Gate Bipolar Transistor packaging structure. The trench IGBT packaging structure includes: a trench IGBT, which includes an emitting electrode metal layer, and a trench gate electrode; a lead frame, which includes a chip placement area and an emitting electrode lead-out end; a first bonding wire connecting the emitting electrode metal layer and an emitting electrode pin. One end of the first bonding wire is connected to a surface, away from the trench gate electrode, of the emitting electrode metal layer to form a strip-shaped first solder joint, the other end is connected to the emitting electrode lead-out end to form a second solder joint, and an extension direction of the first solder joint is perpendicular to an extension direction of the trench of the trench gate electrode.

A semiconductor package comprises a lead frame, a first field-effect transistor (FET), a second low side FET, a first high side FET, a second high side FET, a first metal clip, a second metal clip, and a molding encapsulation. The semiconductor package further comprises an optional integrated circuit (IC) controller or an optional inductor. A method for fabricating a semiconductor package. The method comprises the steps of providing a lead frame; attaching a first low side FET, a second low side FET, a first high side FET, and a second high side FET to the lead frame; mounting a first metal clip and a second metal clip; forming a molding encapsulation; and applying a singulation process.

Contact bumps between a contact pad and a substrate can include a rough surface that can mate with the material of the substrate of which may be flexible. The rough surface can enhance the bonding strength of the contacts, for example, against shear and tension forces, especially for flexible systems such as smart label and may be formed via roller or other methods.