A structure may include a first material, a second material joined to the first material at a junction between the first and second materials, and one or more media extending across the junction to form a continuous interconnect between the first and second materials, wherein the first and second materials are heterogeneous. The structure may further include a transition at the junction between the first and second materials. The one or more media may include a functional material which may be electrically conductive. The structure may further include a third material joined to the second material at a second junction between the second and third materials, the media may extend across the second junction to form a continuous interconnect between the first, second, and third materials, and the second and third materials may be heterogeneous.

One aspect of this disclosure is a power amplifier module that includes a power amplifier, a semiconductor resistor, a tantalum nitride terminated through wafer via, and a conductive layer electrically connected to the power amplifier. The semiconductor resistor can include a resistive layer that includes a same material as a layer of a bipolar transistor of the power amplifier. A portion of the conductive layer can be in the tantalum nitride terminated through wafer via. The conductive layer and the power amplifier can be on opposing sides of a semiconductor substrate. Other embodiments of the module are provided along with related methods and components thereof.

An electronic assembly includes a mechanical carrier, a plurality of integrated circuits disposed on the mechanical carrier, a fan out package disposed on the plurality of integrated circuits, a plurality of singulated substrates disposed on the fan out package, a plurality of electronic components disposed on the plurality of singulated substrates, and at least one stiffness ring disposed on the plurality of singulated substrates. A method for constructing an electronic assembly includes identifying a group of known good singulated substrates, joining the group of known good singulated substrates into a substrate panel, attaching at least one bridge to the substrate panel that electrically couples at least two of the known good singulated substrates, and mounting a plurality of electronic components onto the substrate panel, each electronic component of the plurality of electronic components corresponding to a respective known good singulated substrate.

Described examples include a method having steps of laying out at least two conductors and modeling conductor current through the at least two conductors to determine a current density in the at least two conductors. The method also has steps of revising the at least two conductors as adjusted conductors to add conductive material to areas of the conductor where the modeling conductor current shows above average current density; fabricating the adjusted conductors; and mounting a die to the adjusted conductors.

Described herein are methods and systems for forming metal interconnect layers (MILs) on engineered templates and transferring these MILs to device substrates. This “off-device” approach of forming MILs reduces the complexity and costs of the overall process, allows using semiconductor processes, and reduces the risk of damaging the device substrates. An engineered template is specially configured to release a MIL when the MIL is transferred to a device substrate. In some examples, the engineered template does not include barrier layers and/or adhesion layers. In some examples, the engineered template comprises a conductive portion to assist with selective electroplating. Furthermore, the same engineered template may be reused to form multiple MILs, having the same design. During the transfer, the engineered template and device substrate are stacked together and then separated while the MIL is transitioned from the engineered template to the device substrate.

An interconnect structure includes a dielectric block, a first conductive plug, a second conductive plug, a substrate, a first conductive line, and a second conductive line. The first conductive plug and the second conductive plug are surrounded by the dielectric block. The substrate surrounds the dielectric block. The first conductive line is connected to the first conductive plug and is in contact with a top surface of the dielectric block. The second conductive line is connected to the second conductive plug.

A method for manufacturing a semiconductor structure and the semiconductor structure are provided. The method for manufacturing a semiconductor structure includes: providing an activated region; forming an initial gate located on the activated region; forming a first mask layer on a top surface of the initial gate, in which a first opening penetrating the first mask layer is provided in the first mask layer, and the first opening at least has opposite two sides extending along a first direction; forming sidewall layers located at least on sidewalls of both sides of the first opening extending in the first direction; removing the first mask layer; patterning the initial gate with the sidewall layers on both sides of the first opening as a mask to form gates.

The disclosure concerns method of making a molded substrate, comprising providing a carrier; forming a first conductive layer and first vertical conductive contacts over the carrier; disposing a first layer of encapsulant over the first conductive layer and first vertical conductive contacts; planarizing the first vertical conductive contacts and the first layer of encapsulant to form a first planar surface; forming a second conductive layer and second vertical conductive contacts over the first layer of encapsulant and configured to be electrically coupled with the first conductive layer and first vertical conductive contacts; disposing a second layer of encapsulant over the second conductive layer and second vertical conductive contacts; planarizing the second vertical conductive contacts and the second layer of encapsulant to form a second planar surface; and forming first conductive bumps over the second planar surface, opposite the carrier.

A system and method of using electrochemical additive manufacturing to add interconnection features, such as wafer bumps or pillars, or similar structures like heatsinks, to a plate such as a silicon wafer. The plate may be coupled to a cathode, and material for the features may be deposited onto the plate by transmitting current from an anode array through an electrolyte to the cathode. Position actuators and sensors may control the position and orientation of the plate and the anode array to place features in precise positions. Use of electrochemical additive manufacturing may enable construction of features that cannot be created using current photoresist-based methods. For example, pillars may be taller and more closely spaced, with heights of 200 μm or more, diameters of 10 μm or below, and inter-pillar spacing below 20 μm. Features may also extend horizontally instead of only vertically, enabling routing of interconnections to desired locations.

Methods, systems, and apparatus for reducing power consumption or signal distortions in a semiconductor device package. The semiconductor device package includes a semiconductor device, a first electric path, a second electric path, and an isolation element in the first electric path. The second electric path is electrically connected to the first electric path and a functional unit of the device. The isolation element separates an isolated portion in the first electric path from the second electric path, where the isolation element is configured to reduce current in the isolated portion when a signal is passing through the second electric path.