An electronic component mounting package includes: an insulating base body including a principal face and a recess which opens in the principal face; and a metallic pattern including a plurality of metallic layers lying across a side face of the recess and the principal face. The metallic pattern includes, as an inner layer, at least one metallic layer selected from a tungsten layer, a nickel layer, and a gold layer, and an aluminum layer as an outermost layer. The metallic pattern includes an exposed portion corresponding to a part of the metallic layer constituting the inner layer which part is exposed at the principal face.

A printed circuit board includes: a first insulating layer; a first wiring layer disposed on one surface of the first insulating layer; and a bump at least partially disposed in the first insulating layer and connected to the first wiring layer. The bump at least partially protrudes from the other surface of the first insulating layer, opposite to the one surface of the first insulating layer.

Certain aspects of the present disclosure generally relate to an embedded trace substrate (ETS) with one or more passive components embedded therein. Such an ETS may provide shorter routing, smaller loop area, and lower parasitics between a semiconductor die and a land-side passive component embedded in the ETS. One example embedded trace substrate generally includes a core, a first insulating material disposed above the core and having a first metal pattern embedded therein, a second insulating material disposed below the core and having a second metal pattern embedded therein, and one or more passive components embedded in the core.

A semiconductor package includes a package substrate, a semiconductor chip, connection pins and a molding member. The package substrate includes wiring patterns provided respectively in insulation layers, and has insertion holes extending from an upper surface of the package substrate in a thickness direction that expose portions of the wiring patterns in different insulation layers. The semiconductor chip is disposed on the package substrate, and has a first surface on which chip pads are formed. The connection pins are provided on the chip pads, respectively, and extend through corresponding ones of the insertion holes and electrically connect to the portions of the wiring patterns, respectively, that are exposed by the insertion holes. The molding member is provided on the package substrate to cover the semiconductor chip.

A semiconductor package includes a plurality of inorganic dielectric layers including a plurality of metal interconnect layers formed therein and a plurality of first contact pads, a plurality of organic dielectric layers disposed on and electrically connected to the plurality of inorganic dielectric layers and including a plurality of metal redistribution layers formed therein, wherein the plurality of metal redistribution layers are physically connected to the plurality of first contact pads, and a semiconductor die mounted on the plurality of organic dielectric layers and electrically connected to the plurality of metal redistribution layers through the plurality of metal interconnect layers.

In an embodiment, a structure includes a core substrate, a redistribution structure coupled, the redistribution structure including a plurality of redistribution layers, the plurality of redistribution layers comprising a dielectric layer and a metallization layer, a first local interconnect component embedded in a first redistribution layer of the plurality of redistribution layers, the first local interconnect component comprising conductive connectors, the conductive connectors being bonded to a metallization pattern of the first redistribution layer, the dielectric layer of the first redistribution layer encapsulating the first local interconnect component, a first integrated circuit die coupled to the redistribution structure, a second integrated circuit die coupled to the redistribution structure, an interconnect structure of the first local interconnect component electrically coupling the first integrated circuit die to the second integrated circuit die, and a set of conductive connectors coupled to a second side of the core substrate.

A circuit assembly may include a substrate and a pattern of contact points formed from deformable conductive material supported by the substrate. The assembly may further include an electric component supported by the substrate and having terminals arranged in a pattern corresponding to the pattern of contacts points. The one or more of the terminals of the electric component may contact one or more of the corresponding contact points to form one or more electrical connections between the electric component and the contact points.

A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a redistribution structure, conductive joints, conductive terminals, a circuit substrate, and an insulating encapsulation. The redistribution structure includes a first side and a second side opposite to the first side, wherein trenches are located on the second side of the redistribution structure and extend to an edge of the second side of the redistribution structure. The conductive joints are disposed over the first side of the redistribution structure. The conductive terminals are disposed over the second side of the redistribution structure. The circuit substrate electrically coupled to the redistribution structure through the conductive joints. The insulating encapsulation is disposed on the first side of the redistribution structure to cover the circuit substrate.

Electrical interconnect technology for a package substrate is disclosed. A substrate can include a first conductive element at least partially disposed in a first routing layer, and a second conductive element at least partially disposed in a second routing layer. The first and second routing layers are adjacent routing layers. The substrate can also include a third conductive element having first and second portions disposed in the first routing layer, and an intermediate third portion disposed in a “sub-interconnect layer” between the first and second routing layers.

A method for manufacturing a circuit redistribution structure includes the following steps. A first dielectric is formed on a carrier. Conductive blind vias are formed in the first dielectric. A first circuit redistribution layer is formed on the first dielectric. A second dielectric is formed on the first dielectric. First and second holes are formed on the second dielectric. A trench is formed in the second dielectric to divide the second dielectric into first and second portions. A first portion of the first circuit redistribution layer and the first hole are disposed in the first portion of the second dielectric, and a second portion of the first circuit redistribution layer and the second hole are disposed in the second portion of the second dielectric. Conductive blind vias are formed in the first and second holes, and a second circuit redistribution layer is formed on the second dielectric.