A z-disaggregated integrated circuit package substrate assembly comprises a first substrate component (a coreless patch), a second substrate component (a core patch), and a third substrate component (an interposer). The coreless patch comprises thinner dielectric layers and higher density routing and can comprise an embedded bridge to allow for communication between integrated circuit dies attached to the coreless patch. The core layer acts as a middle layer interconnect between the coreless patch and the interposer and comprises liquid metal interconnects to connect the core patch physically and electrically to the coreless patch and the interposer. Core patch through holes comprise liquid metal plugs. Some through holes can be surrounded by and coaxially aligned with magnetic plugs to provide improved power signal delivery. The interposer comprises thicker dielectric layers and lower density routing. The substrate assembly can reduce cost and provide improved overall yield and electrical performance relative to monolithic substrates.

An integrated circuit package and a method of forming the same are provided. A method includes forming a conductive column over a carrier. An integrated circuit die is attached to the carrier, the integrated circuit die being disposed adjacent the conductive column. An encapsulant is formed around the conductive column and the integrated circuit die. The carrier is removed to expose a first surface of the conductive column and a second surface of the encapsulant. A polymer material is formed over the first surface and the second surface. The polymer material is cured to form an annular-shaped structure. An inner edge of the annular-shaped structure overlaps the first surface in a plan view. An outer edge of the annular-shaped structure overlaps the second surface in the plan view.

Embodiments include forming a die, the die including a pad and a passivation layer over the pad. A via is formed to the pad through the passivation layer. A solder cap is formed on the via, where a first material of the solder cap flows to the sidewall of the via. In some embodiments, the via is encapsulated in a first encapsulant, where the first encapsulant is a polymer or molding compound selected to have a low co-efficient of thermal expansion and/or low curing temperature. In some embodiments, the first material of the solder cap is removed from the sidewall of the via by an etching process and the via is encapsulated in a first encapsulant.

An embodiment is a method including: attaching a first die to a first side of a first component using first electrical connectors, attaching a first side of a second die to first side of the first component using second electrical connectors, attaching a dummy die to the first side of the first component in a scribe line region of the first component, adhering a cover structure to a second side of the second die, and singulating the first component and the dummy die to form a package structure.

A semiconductor chip is arranged on a region of laser direct structuring (LDS) material of a laminar substrate. The semiconductor chip has a front active area facing towards, and a metallized back surface facing away from, the laminar substrate. An encapsulation of LDS material on the laminar substrate encapsulates the semiconductor chip with the metallized back surface of the semiconductor chip exposed at an outer surface of the encapsulation of LDS material. Electrically conductive lines and first vias are structured in the region of LDS material to electrically connect to the front active area of the semiconductor chip. A thermally conductive layer is plated over the outer surface of the encapsulation of LDS material in contact with the metallized back surface of the semiconductor chip. A heat extractor body of thermally conductive material is coupled in heat transfer relationship with the thermally conductive layer.

Semiconductor devices and methods of forming the same are provided. A method according to the present disclosure includes forming a first wafer including a plurality of electronic integrated circuits (EICs), forming a second wafer including a plurality of photonic integrated circuits (PICs), bonding the first wafer to the second wafer to form a first stacked wafer. The bonding of the first wafer to the second wafer includes vertically aligning each of the plurality of the EICs with one of the plurality of the PICs.

A semiconductor device includes a power module, a circuit package, and a joint portion joining the power module and the circuit package. The circuit package includes a semiconductor element, a wiring layer electrically connected with the semiconductor element, a heat conductive member, and a second mold resin portion sealing the semiconductor element and the heat conductive member. The wiring layer includes a connecting portion connected with the heat conductive member. One of the connecting portion or the heat conductive member is joined with a signal wire in the power module via the joint portion. The heat conductive member penetrates the second mold resin portion in a thickness direction of the semiconductor element. The heat conductive member and the connecting portion are arranged in a straight line in the thickness direction of the semiconductor element.

A method of forming a semiconductor structure includes the following operations. A first conductive structure is formed on a first side of a first glass carrier. A second glass carrier is bonded to the first conductive structure. Conductive vias are formed to penetrate through the first glass carrier, and the conductive vias are electrically connected to the first conductive structure. A second conductive structure is formed on a second side of the first glass carrier opposite to the first side, and the second conductive structure is electrically connected to the conductive vias.

A semiconductor device including an interposer including a central region and an edge region entirely surrounding the central region, wherein the interposer includes a wiring structure disposed in the first region and a metal structure disposed continuously within the entirety of the second region, a first semiconductor chip mounted in the central region and connected to the wiring structure, and a second semiconductor chip mounted in the central region adjacent to the first semiconductor chip and connected to the second wiring structure.

Embodiments disclosed herein comprise package substrates and methods of forming package substrates. In an embodiment, a package substrate comprises a core substrate. A hole is disposed into the core substrate, and a via is disposed in the hole. In an embodiment, the via completely fills the hole. In an embodiment, a method of forming a package substrate comprises exposing a region of a core substrate with a laser. In an embodiment, the laser changes the morphology of the exposed region. The method may further comprise etching the core substrate, where the exposed region etches at a faster rate than the remainder of the core substrate to form a hole in the core substrate. The method may further comprise disposing a via in the hole.