Disclosed herein are cavity structures in integrated circuit (IC) package supports, as well as related methods and apparatuses. For example, in some embodiments, an IC package support may include: a cavity in a dielectric material, wherein the cavity has a bottom and sidewalls; conductive contacts at the bottom of the cavity, wherein the conductive contacts include a first material; a first peripheral material outside the cavity, wherein the first peripheral material is at the sidewalls of the cavity and proximate to the bottom of the cavity, and the first peripheral material includes the first material; and a second peripheral material outside the cavity, wherein the second peripheral material is at the sidewalls of the cavity and on the first peripheral material, and the second peripheral material is different than the first peripheral material.

A 3D-IC includes a first tier device and a second tier device. The first tier device and the second tier device are vertically stacked together. The first tier device includes a first substrate and a first interconnect structure formed over the first substrate. The second tier device includes a second substrate, a doped region formed in the second substrate, a dummy gate formed over the substrate, and a second interconnect structure formed over the second substrate. The 3D-IC also includes an inter-tier via extends vertically through the second substrate. The inter-tier via has a first end and a second end opposite the first end. The first end of the inter-tier via is coupled to the first interconnect structure. The second end of the inter-tier via is coupled to one of: the doped region, the dummy gate, or the second interconnect structure.

An electronic component mounting package includes: an insulating base body including a principal face and a recess which opens in the principal face; and a metallic pattern including a plurality of metallic layers lying across a side face of the recess and the principal face. The metallic pattern includes, as an inner layer, at least one metallic layer selected from a tungsten layer, a nickel layer, and a gold layer, and an aluminum layer as an outermost layer. The metallic pattern includes an exposed portion corresponding to a part of the metallic layer constituting the inner layer which part is exposed at the principal face.

A semiconductor package includes a package substrate, a semiconductor chip, connection pins and a molding member. The package substrate includes wiring patterns provided respectively in insulation layers, and has insertion holes extending from an upper surface of the package substrate in a thickness direction that expose portions of the wiring patterns in different insulation layers. The semiconductor chip is disposed on the package substrate, and has a first surface on which chip pads are formed. The connection pins are provided on the chip pads, respectively, and extend through corresponding ones of the insertion holes and electrically connect to the portions of the wiring patterns, respectively, that are exposed by the insertion holes. The molding member is provided on the package substrate to cover the semiconductor chip.

A semiconductor device structure includes a package substrate having a first side and a second side, a first stacking via formed within the package substrate, a second stacking via formed within the package substrate, and a first semiconductor die attached to the first side of the package substrate and electrically coupled to the first stacking via. The semiconductor device structure includes a second semiconductor die attached to the first side of the package substrate and electrically coupled to the second stacking via; and a bridge die attached to the second side of the package substrate and electrically coupled to the first stacking via and the second stacking via through first stacking via, the bridge die, and the second stacking via.

A circuit assembly may include a substrate and a pattern of contact points formed from deformable conductive material supported by the substrate. The assembly may further include an electric component supported by the substrate and having terminals arranged in a pattern corresponding to the pattern of contacts points. The one or more of the terminals of the electric component may contact one or more of the corresponding contact points to form one or more electrical connections between the electric component and the contact points.

A transient electronic device utilizes a glass-based interposer that is treated using ion-exchange processing to increase its fragility, and includes a trigger device operably mounted on a surface thereof. An integrated circuit (IC) die is then bonded to the interposer, and the interposer is mounted to a package structure where it serves, under normal operating conditions, to operably connect the IC die to the package I/O pins/balls. During a transient event (e.g., when unauthorized tampering is detected), a trigger signal is transmitted to the trigger device, causing the trigger device to generate an initial fracture force that is applied onto the glass-based interposer substrate. The interposer is configured such that the initial fracture force propagates through the glass-based interposer substrate with sufficient energy to both entirely powderize the interposer, and to transfer to the IC die, whereby the IC die also powderizes (i.e., visually disappears).

A semiconductor device and a method of making the same are provided. A first die and a second die are placed over a carrier substrate. A first molding material is formed adjacent to the first die and the second die. A first redistribution layer is formed overlying the first molding material. A through via is formed over the first redistribution layer. A package component is on the first redistribution layer next to the copper pillar. The package component includes a second redistribution layer. The package component is positioned so that it overlies both the first die and the second die in part. A second molding material is formed adjacent to the package component and the first copper pillar. A third redistribution layer is formed overlying the second molding material. The second redistribution layer is placed on a substrate and bonded to the substrate.

Electrical interconnect technology for a package substrate is disclosed. A substrate can include a first conductive element at least partially disposed in a first routing layer, and a second conductive element at least partially disposed in a second routing layer. The first and second routing layers are adjacent routing layers. The substrate can also include a third conductive element having first and second portions disposed in the first routing layer, and an intermediate third portion disposed in a “sub-interconnect layer” between the first and second routing layers.

A process comprises bonding a semiconductor wafer to an inorganic wafer. The semiconductor wafer is opaque to a wavelength of light to which the inorganic wafer is transparent. After the bonding, a damage track is formed in the inorganic wafer using a laser that emits the wavelength of light. The damage track in the inorganic wafer is enlarged to form a hole through the inorganic wafer by etching. The hole terminates at an interface between the semiconductor wafer and the inorganic wafer. An article is also provided, comprising a semiconductor wafer bonded to an inorganic wafer. The semiconductor wafer is opaque to a wavelength of light to which the inorganic wafer is transparent. The inorganic wafer has a hole formed through the inorganic wafer. The hole terminates at an interface between the semiconductor wafer and the inorganic wafer.