The present disclosure relates to thin-form-factor reconstituted substrates and methods for forming the same. The reconstituted substrates described herein may be utilized to fabricate homogeneous or heterogeneous high-density 3D integrated devices. In one embodiment, a silicon substrate is structured by direct laser patterning to include one or more cavities and one or more vias. One or more semiconductor dies of the same or different types may be placed within the cavities and thereafter embedded in the substrate upon formation of an insulating layer thereon. One or more conductive interconnections are formed in the vias and may have contact points redistributed to desired surfaces of the reconstituted substrate. The reconstituted substrate may thereafter be integrated into a stacked 3D device.

Semiconductor devices having electrical interconnections through vertically stacked semiconductor dies, and associated systems and methods, are disclosed herein. In some embodiments, a semiconductor assembly includes a die stack having a plurality of semiconductor dies. Each semiconductor die can include surfaces having an insulating material, a recess formed in at least one surface, and a conductive pad within the recess. The semiconductor dies can be directly coupled to each other via the insulating material. The semiconductor assembly can further include an interconnect structure electrically coupled to each of the semiconductor dies. The interconnect structure can include a monolithic via extending continuously through each of the semiconductor dies in the die stack. The interconnect structure can also include a plurality of protrusions extending from the monolithic via. Each protrusion can be positioned within the recess of a respective semiconductor die and can be electrically coupled to the conductive pad within the recess.

Disclosed is a strip substrate including a dielectric layer that has a plurality of unit regions spaced apart from each other in a first direction and a saw line region between the unit regions, a plurality of conductive dummy patterns on corresponding unit regions of the dielectric layer, a plurality of saw line patterns on the saw line region of the dielectric layer and extending in a second direction that intersects the first direction, and a protection pattern that covers the dielectric layer. Ends of the conductive dummy patterns are spaced apart from each other in a direction parallel to the first direction. Ends of the saw line patterns are spaced apart from each other in a direction parallel to the second direction. The protection pattern is between the ends of the conductive dummy patterns and between the ends of the saw line patterns.

A method comprises embedding a semiconductor structure in a molding compound layer, depositing a plurality of photo-sensitive material layers over the molding compound layer, developing the plurality of photo-sensitive material layers to form a plurality of openings, wherein a first portion and a second portion of an opening of the plurality of openings are formed in different photo-sensitive material layers and filling the first portion and the second portion of the opening with a conductive material to form a first via in the first portion and a first redistribution layer in the second portion.

A package substrate and package assembly including a package substrate including a substrate body including electrical routing features therein and a surface layer and a plurality of first and second contact points on the surface layer including a first pitch and a second pitch, respectively, wherein the plurality of first contact points and the plurality of second contact points are continuous posts to the respective ones of the electrical routing features. A method including forming first conductive vias in a package assembly, wherein the first conductive vias include substrate conductive vias to electrical routing features in a package substrate and bridge conductive vias to bridge surface routing features of a bridge substrate; forming a first surface layer and a second surface layer on the package substrate; and forming second conductive vias through each of the first surface layer and the second surface layer to the bridge conductive vias.

This application discloses a chip package assembly, an electronic device, and a preparation method of a chip package assembly. The chip package assembly includes a package substrate, a chip, and a heat dissipation part. The package substrate includes an upper conductive layer, a lower conductive layer, and a conductive part connected between the upper conductive layer and the lower conductive layer. The chip includes a front electrode and a back electrode that are disposed opposite each other, the chip is embedded in the package substrate, the conductive part surrounds the chip, the front electrode is connected to the lower conductive layer, and the back electrode is connected to the upper conductive layer. The heat dissipation part is connected to a surface of the upper conductive layer that is away from the chip. The upper conductive layer, the lower conductive layer, and the conductive part each conduct heat.

A flexible sensing device includes a flexible substrate selected from a bismaleimide-triazine resin substrate, an ajinomoto build-up film substrate, and a polyimide film substrate. A plurality of first sensing stripes are formed on the flexible substrate and are spaced apart from each other in a first direction. A dielectric film is superposed on the first sensing stripes. A plurality of second sensing stripes are formed on the dielectric film and are spaced apart from each other in a second direction. Each second sensing stripe crosses over the first sensing stripes and is spaced apart from the first sensing stripes by the dielectric film. A method of making the same is also disclosed.

A method of forming a semiconductor device includes providing a substrate that comprises a metal region, forming an encapsulant body of electrically insulating material on an upper surface of the metal region, forming an opening in the encapsulant body, and inserting a press-fit connector into the opening, wherein after inserting the press-fit connector into the opening, the press-fit connector is securely retained to the substrate and an interfacing end of the press-fit connector is electrically accessible.

A die dipping structure includes a plate including a first recessed portion having a first depth and filled with a first flux material. The plate further includes a second recessed portion, isolated from the first recessed portion, with a second depth and filled with a second flux material. The second depth is different from the first depth. The die dipping structure further includes a motor configured to move the plate so as to simultaneously dip a first die and a second die into the flux of the first recessed portion and the flux of the second recessed portion, respectively.

Disclosed are wiring substrates, methods of fabricating the same, and methods of fabricating semiconductor packages. The wiring substrate includes a dielectric layer that includes a plurality of unit regions, a sawing region that surrounds each of the unit regions, and an edge region that surrounds the unit regions and the sawing region, a first upper protection pattern on a top surface of the dielectric layer on the unit regions and the sawing region, and a second upper protection pattern on a top surface of the dielectric layer on the edge region. The second upper protection pattern surrounds the first upper protection pattern when viewed in plan and includes a dielectric material different from a dielectric material of the first upper protection pattern.