A method of manufacturing a semiconductor package including coating a flux on a connection pad provided on a first surface of a substrate, the flux including carbon nanotubes (CNTs), placing a solder ball on the connection pad coated with the flux, forming a solder layer attached to the connection pad from the solder ball through a reflow process, and mounting a semiconductor chip on the substrate such that the solder layer faces a connection pad in the semiconductor chip may be provided.

Disclosed herein are methods of fabricating a packaged radio-frequency (RF) device. The disclosed methods use a film during fabrication to control the distribution of an under-fill material between one or more components and a packaging substrate. The method includes mounting components to a first side of a packaging substrate and applying a film to a second side of a packaging substrate. The method also includes mounting a lower component to the second side of the packaging substrate and under-filling the lower component mounted on the second side of the packaging substrate with an under-filling agent. The method also includes removing the film on the second side of the packaging substrate and mounting solder balls to the second side of the packaging substrate after removal of the film.

A first insulation layer comprising stacked prepreg layers is provided, and a metallic protective layer is formed on the first insulation layer. A first alignment mark is formed on the first insulation layer, and an accommodation cavity is formed in the first insulation layer according to the first alignment mark. A second alignment mark is formed on the first insulation layer according to the first alignment mark. A carrier plate is attached on the first insulation layer through a thermal release tape layer, and the semiconductor device is temporarily fixed on the thermal release tape layer within the accommodation cavity according to the second alignment mark. A semi-cured second insulation layer is placed over the first insulation layer, and the second insulation layer is laminated and cured. A re-distribution layer is formed on the second insulation layer, and the re-distribution layer is electrically connected with the semiconductor device.

A method of fabricating a connection structure is disclosed. The method includes providing a substrate that has a top surface and includes a set of pads for soldering, each of which has a pad surface exposed from the top surface of the substrate. The method also includes applying a surface treatment to a part of the top surface of the substrate close to the pads and the pad surface of each pad so as to make at least the part of the top surface and the pad surfaces of the pads rougher. The surface treatment includes sandblasting.

The present disclosure relates to thin-form-factor reconstituted substrates and methods for forming the same. The reconstituted substrates described herein may be utilized to fabricate homogeneous or heterogeneous high-density 3D integrated devices. In one embodiment, a silicon substrate is structured by direct laser patterning to include one or more cavities and one or more vias. One or more semiconductor dies of the same or different types may be placed within the cavities and thereafter embedded in the substrate upon formation of an insulating layer thereon. One or more conductive interconnections are formed in the vias and may have contact points redistributed to desired surfaces of the reconstituted substrate. The reconstituted substrate may thereafter be integrated into a stacked 3D device.

A method for isolating at least one conductive via from a surrounding glass substrate is provided. A support layer is formed over at least one surface of the glass substrate. Thereafter, the glass substrate is removed. As a result, the at least one conductive via can be analyzed without interference from the glass substrate.

Described herein are methods of manufacturing dual-sided packaged electronic modules to control the distribution of an under-fill material between one or more components and a packaging substrate. The disclosed technologies include using a dam on a packaging substrate that is configured to prevent or limit the flow of a capillary under-fill material. This can prevent or limit the capillary under-fill material from flowing onto or contacting other components or elements on the packaging substrate, such as solder balls of a ball-grid array. Accordingly, the disclosed technologies control under-fill for dual-sided ball grid array packages using a dam on a packaging substrate.

A method of fabricating a semiconductor package includes forming a capping pattern on a chip pad of a semiconductor device. The semiconductor device includes a passivation pattern that exposes a portion of the chip pad, and the capping pattern covers the chip pad. The method further includes forming a redistribution layer on the capping pattern. Forming the redistribution layer includes forming a first insulation pattern on the capping pattern and the passivation pattern, forming a first opening in the first insulation pattern by performing exposure and development processes on the first insulation pattern, in which the first opening exposes a portion of the capping pattern, and forming a redistribution pattern in the first opening.

A method includes picking up a first package component, removing an oxide layer on an electrical connector of the first package component, placing the first package component on a second package component after the oxide layer is removed, and bonding the first package component to the second package component.

A method for manufacturing an inductor built-in substrate includes forming openings in a core substrate including a resin substrate and a metal foil laminated on the resin substrate, filling a magnetic resin in the openings formed in the substrate, forming a shield layer including a first plating film on the substrate and on a surface of the magnetic resin such that the shielding layer is formed on the metal foil and on the surface of the magnetic resin, forming first through holes in the substrate, applying a desmear treatment in the first through holes, forming second through holes in the magnetic resin after the desmear treatment, and forming a second plating film on the substrate, on the magnetic resin, and in the first and second through holes such that the second plating film is formed on the shield layer, in the first through holes, and in the second through holes.