A power semiconductor substrate comprising an insulating planar base, at least one conductor track and at least one contact area as part of the conductor track, wherein a layer of a metallic material is disposed on the contact area by means of pressure sintering. The associated method comprises the steps of: producing a power semiconductor substrate that includes a planar insulating base, conductor tracks and contact areas; arranging a pasty layer, composed of a metallic material and a solvent, on at least one contact area of the power semiconductor substrate; and applying pressure to the pasty layer.

A method of making an electronic device includes forming a circuit layer on a liquid crystal polymer (LCP) substrate and having at least one solder pad. The method also includes forming an LCP solder mask having at least one aperture therein alignable with the at least one solder pad. The method further includes aligning and laminating the LCP solder mask and the LCP substrate together, then positioning solder paste in the at least one aperture. At least one circuit component may then be attached to the at least one solder pad using the solder paste.

A module 1a includes an electronic component 3a, and also includes a wiring substrate 2 on one principal surface of which the electronic component 3a is mounted and in which a radiator 4 for dissipating heat generated from the electronic component 3 is provided. The radiator 4 includes a heat dissipation section 4a that is provided so that a part thereof is exposed to a side surface of the wiring substrate 2. In this case, because the heat dissipation section 4a is provided so that a part thereof is exposed to the side surface of the wiring substrate 2, the heat from the electronic component 3a can be dissipated through the side surface of the wiring substrate 2.

Disclosed is a ceramic substrate manufacturing method in which a copper sheet is etched and then bonded to a ceramic substrate, so that the ceramic substrate has reduced to overall processing time and improved reliability and product lifespan. The disclosed ceramic substrate manufacturing method comprises the steps of: etching a copper sheet so as to prepare a metal substrate; etching a ceramic substrate so as to prepare a unit ceramic substrate; assembling the metal substrate and the unit ceramic substrate; bonding the metal substrate and the unit ceramic substrate so as to form a stack; partially printing a metal paste on the surface of the stack; and sintering the metal paste.

Embodiments may relate to a microelectronic package comprising: a die and a package substrate coupled to the die with a first interconnect on a first face. The package substrate comprises: a second interconnect and a third interconnect on a second face opposite to the first face; a conductive signal path between the first interconnect and the second interconnect; a conductive ground path between the second interconnect and the third interconnect; and an electrostatic discharge (ESD) protection material coupled to the conductive ground path. The ESD protection material comprises a first electrically-conductive carbon allotrope having a first functional group, a second electrically-conductive carbon allotrope having a second functional group, and an electrically-conductive polymer chemically bonded to the first functional group and the second functional group permitting an electrical signal to pass between the first and second electrically-conductive carbon allotropes.

The invention relates to a module (1) in which voltages greater than 1,000 V and currents greater than 100 A are applied via supply lines, with an electrically insulating carrier (2), with a connection means (3) which has a material thickness greater than 0.3 mm and is connected to the carrier (2) via a metallization area (4) which is delimited by a first end (23) and a second end (24), with electronic components (19, 20) which are connected to the connection means (3) as required, and with cooling means (14).

In order that the power is supplied from the outside via the connection means (3) directly to the module and thus the bonding processes that are customary in the prior art are omitted and parasitic inductances on the power supply are avoided, the invention proposes that the connection means (3) protrudes beyond one end (23, 24) of the metallization area (4) at least at one point, is not fixed to the carrier (2) in this area (9) and has contact means (22).

A bottom side interposer provides a structurally balanced chip carrier module to reduce thermal warp and increase package robustness. The bottom side interposer is attached to the bottom of a chip carrier which carries semiconductor chips on the top side of the chip carrier. The top side of the chip carrier typically includes a top side interposer between the semiconductor chips and the chip carrier. The bottom side interposer has a coefficient of thermal expansion (CTE) that is similar to the chips and top side interposer, or tailored to have a CTE intermediate to the chips and the chip carrier. Pads on the bottom side interposer may be plated or fitted with solder balls to complete the module so the module can be connected to a printed circuit board.

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a semiconductor die laterally covered by an insulating encapsulation, a first redistribution structure disposed on the semiconductor die and the insulating encapsulation, a second redistribution structure disposed opposite to the first redistribution structure, and a through insulating via (TIV) penetrating through the insulating encapsulation. The semiconductor die is electrically coupled to the first redistribution structure through the second redistribution structure and the TIV. The first redistribution structure includes a patterned conductive layer covered by a patterned dielectric layer, and under-ball metallurgy (UBM) pattern partially covered by the patterned dielectric layer. A first portion of the UBM pattern physically contacts a via portion of the patterned conductive layer which is tapered toward the UBM pattern, and a second portion of the UBM pattern is connected to the first portion and protruded from the patterned dielectric layer.

In described examples, a semiconductor wafer with a thermally conductive surface layer comprises a bulk semiconductor layer having a first surface and a second surface, circuitry on the first surface, a metallic layer attached to the first surface or the second surface, and a graphene layer attached to the metallic layer. The first surface opposes the second surface. The metallic layer comprises a transition metal.

Techniques for fabricating a semiconductor package having magnetic materials embedded therein are described. For one technique, fabrication of package includes: forming a pad and a conductive line on a build-up layer; forming a raised pad structure on the build-up layer, the raised pad comprising a pillar structure on the pad; encapsulating the conductive line and the raised pad structure in a magnetic film comprising one or more magnetic fillers; planarizing a top surface of the magnetic film until top surfaces of the raised pad structure and the magnetic film are co-planar; depositing a primer layer on the top surfaces; removing one or more portions of the primer layer above the raised pad structure to create an opening; and forming a via in the opening on the raised pad structure. The primer layer may comprise one or more of a build-up layer, a photoimageable dielectric layer, and a metal mask.