A power semiconductor module arrangement includes: a base plate; substrates arranged on a first surface of the base plate; a connection layer arranged between a different one of the substrates and the base plate and permanently attaching the respective substrate to the base plate; and a spacer arranged between one of the substrates and the base plate and embedded in a material of the respective connection layer. For at least one substrate: either no spacer or one or more of a first kind of spacers having a first height in a vertical direction perpendicular to the first surface of the base plate is arranged below a first half of the respective substrate, and one or more of a second kind of spacers having a second height in the vertical direction is arranged below a second half of the respective substrate, the second height being greater than the first height.

Direct-bonded native interconnects and active base dies are provided. In a microelectronic architecture, active dies or chiplets connect to an active base die via their core-level conductors. These native interconnects provide short data paths, which forgo the overhead of standard interfaces. The system saves redistribution routing as the native interconnects couple in place. The base die may contain custom logic, allowing the attached dies to provide stock functions. The architecture can connect diverse interconnect types and chiplets from various process nodes, operating at different voltages. The base die may have state elements for drive. Functional blocks aboard the base die receive native signals from diverse chiplets, and communicate with all attached chiplets. The chiplets may share processing and memory resources of the base die. Routing blockages are minimal, improving signal quality and timing. The system can operate at dual or quad data rates. The architecture facilitates ASIC, ASSP, and FPGA ICs and neural networks, reducing footprint and power requirements.

Embodiments include semiconductor packages. A semiconductor package include a high-power electronic component and an embedded heat spreader (EHS) in a package substrate. The EHS is adjacent to the high-power electronic component. The semiconductor package includes a plurality of thermal interconnects below the EHS and the package substrate, and a plurality of dies on the package substrate. The thermal interconnects is coupled to the EHS. The EHS is below the high-power electronic component and embedded within the package substrate. The high-power electronic component has a bottom surface substantially proximate to a top surface of the EHS. The EHS is a copper heat sink, and the high-power electronic component is an air core inductor or a voltage regulator. The thermal interconnects are comprised of thermal ball grid array balls or thermal adhesive materials. The thermal interconnects couple a bottom surface of the package substrate to a top surface of a substrate.

Disclosed is a chip heat dissipating structure, a process and a semiconductor device. The structure includes at least a chip and a package layer, the package layer encapsulates the chip, an intermediate structure for buffering temperature-varying stress generated by an internal structure of the package layer and conducting internal heat is arranged in the package layer. In present disclosure, heat generated by chip silicon is transmitted to each heat conductive protrusion through the intermediate heat conductive layer, then heat dissipation is realized through heat fin. The heat fin cooperates with the bonding pad to form double-sided heat dissipation, with good heat dissipation effect, stress deformation of the heat fin does not directly extrude the chip to avoid damage. Structure of both sides of the chip is relatively symmetrical, which balances a stress effect caused by high and low temperatures. Device has strong reliability, and production cost is low.

An integrated circuit includes a substrate and a semiconductor material layer over the substrate. The integrated circuit includes a first source structure in the semiconductor material layer. The first source structure includes a first doped well. The integrated circuit includes a drain structure in the semiconductor material layer. The drain structure includes a second doped well. The integrated circuit includes a second source structure in the semiconductor material layer. The second source structure includes a third doped well. The drain structure is between the first source structure and the second source structure. The integrated circuit includes a first deep trench isolation (DTI) extending through the first doped well; and a first thermal contact extending through the first DTI. The thermal contact is in direct contact with the substrate. The first DTI is between the thermal contact and the first doped well.

A method for mounting an electrical component on a substrate is disclosed. According to the method, joining is simplified using a cover, or hood, that includes a contact structure on an inner side of the hood, wherein when the hood is mounted, the contact structure is joined to the underlying structure at different joining levels simultaneously using an additional material. Moreover, a joining pressure, e.g., for diffusion or sintered bonds for electrical contacts, can be applied using such a hood.

Direct-bonded native interconnects and active base dies are provided. In a microelectronic architecture, active dies or chiplets connect to an active base die via their core-level conductors. These native interconnects provide short data paths, which forgo the overhead of standard interfaces. The system saves redistribution routing as the native interconnects couple in place. The base die may contain custom logic, allowing the attached dies to provide stock functions. The architecture can connect diverse interconnect types and chiplets from various process nodes, operating at different voltages. The base die may have state elements for drive. Functional blocks aboard the base die receive native signals from diverse chiplets, and communicate with all attached chiplets. The chiplets may share processing and memory resources of the base die. Routing blockages are minimal, improving signal quality and timing. The system can operate at dual or quad data rates. The architecture facilitates ASIC, ASSP, and FPGA ICs and neural networks, reducing footprint and power requirements.

A method embodiment includes forming a patterned first photo resist over a seed layer. A first opening in the patterned first photo resist exposes the seed layer. The method further includes plating a first conductive material in the first opening on the seed layer, removing the patterned first photo resist, and after removing the patterned first photo resist, forming a patterned second photo resist over the first conductive material. A second opening in the patterned second photo resist exposes a portion of the first conductive material. The method further includes plating a second conductive material in the second opening on the first conductive material, removing the patterned second photo resist, and after removing the patterned second photo resist, depositing a dielectric layer around the first conductive material and the second conductive material.

A power semiconductor module includes a substrate, having power semiconductor components, further including a housing element, and having a DC voltage connection device having a flat lead connection device and a second flat lead connection element, wherein the flat lead connection device has a first flat lead connection element encased by a plastic element of the flat lead connection device and materially bonded to the plastic element, wherein a connection section of the first flat lead connection element projects from the plastic element, a connection section of the second flat lead connection element is arranged on the plastic element or is at least partly enclosed by the plastic element and bonded to the plastic element so that a section of the plastic element is between the first flat lead connection element and the connection section of the second flat lead connection element.

In one example, a semiconductor device comprises an electronic component comprising a component face side, a component base side, a component lateral side connecting the component face side to the component base side, and a component port adjacent to the component face side, wherein the component port comprises a component port face. A clip structure comprises a first clip pad, a second clip pad, a first clip leg connecting the first clip pad to the second clip pad, and a first clip face. An encapsulant covers portions of the electronic component and the clip structure. The encapsulant comprises an encapsulant face, the first clip pad is coupled to the electronic component, and the component port face and the first clip face are exposed from the encapsulant face. Other examples and related methods are also disclosed herein.