Direct-bonded native interconnects and active base dies are provided. In a microelectronic architecture, active dies or chiplets connect to an active base die via their core-level conductors. These native interconnects provide short data paths, which forgo the overhead of standard interfaces. The system saves redistribution routing as the native interconnects couple in place. The base die may contain custom logic, allowing the attached dies to provide stock functions. The architecture can connect diverse interconnect types and chiplets from various process nodes, operating at different voltages. The base die may have state elements for drive. Functional blocks aboard the base die receive native signals from diverse chiplets, and communicate with all attached chiplets. The chiplets may share processing and memory resources of the base die. Routing blockages are minimal, improving signal quality and timing. The system can operate at dual or quad data rates. The architecture facilitates ASIC, ASSP, and FPGA ICs and neural networks, reducing footprint and power requirements.

Direct-bonded native interconnects and active base dies are provided. In a microelectronic architecture, active dies or chiplets connect to an active base die via their core-level conductors. These native interconnects provide short data paths, which forgo the overhead of standard interfaces. The system saves redistribution routing as the native interconnects couple in place. The base die may contain custom logic, allowing the attached dies to provide stock functions. The architecture can connect diverse interconnect types and chiplets from various process nodes, operating at different voltages. The base die may have state elements for drive. Functional blocks aboard the base die receive native signals from diverse chiplets, and communicate with all attached chiplets. The chiplets may share processing and memory resources of the base die. Routing blockages are minimal, improving signal quality and timing. The system can operate at dual or quad data rates. The architecture facilitates ASIC, ASSP, and FPGA ICs and neural networks, reducing footprint and power requirements.

A power semiconductor module arrangement includes: a base plate; a contact element configured to, when the base plate is arranged in a housing, provide an electrical connection between an inside and an outside of the housing; an electrically insulating first layer connected to the base plate, the contact element being connected to the electrically insulating first layer; a third layer on the base plate or on the electrically insulating first layer; and a second layer on the electrically insulating first layer or on the contact element. The electrically insulating first layer is mounted on the base plate such that the third layer attaches the electrically insulating first layer to the base plate. The contact element is mounted on the electrically insulating first layer such that the second layer attaches the contact element to the electrically insulating first layer.

According to the present invention, a semiconductor device includes a substrate having a metallic pattern formed on a top surface of the substrate, a semiconductor chip provided on the metallic pattern, a back surface electrode terminal in flat plate form connected to the metallic pattern with a wire, a front surface electrode terminal in flat plate form, the front surface electrode terminal being in parallel to the back surface electrode terminal above the back surface electrode terminal, extending immediately above the semiconductor chip, and being directly joined to a top surface of the semiconductor chip, a case surrounding the substrate and a seal material for sealing an inside of the case.

A package structure and the method thereof are provided. The package structure includes a conductive plate, a semiconductor die, a molding compound, and antenna elements. The conductive plate has a first surface, a second surface and a sidewall connecting the first surface and the second surface. The semiconductor die is located on the second surface of the conductive plate. The molding compound laterally encapsulates the semiconductor die and covers the sidewall and a portion of the second surface exposed by the semiconductor die, wherein the first surface of the conductive plate is coplanar with a surface of the molding compound. The antenna elements are located over the first surface of the conductive plate.

A conductive thin-film thinner than the undersurface electrode is provided outside the undersurface electrode on the undersurface of the ceramic substrate and connected to the undersurface electrode. A length from an outer circumferential part of the undersurface electrode to an outer circumferential pert of the ceramic substrate is equal to a length from an outer circumferential part of the top surface electrode to an outer circumferential part of the ceramic substrate. A thickness of the conductive thin-film is half or less than a thickness of the ceramic substrate.

An electronic device module includes a substrate, a first device and a second device mounted on the substrate, and a shielding frame mounted on the substrate to accommodate the first device. The shielding frame includes a heat dissipating portion stacked on the first device, and posts extended from an edge of the heat dissipating portion and spaced apart from each other. A spacing distance between the posts is smaller than a wavelength of an electromagnetic wave introduced into the first device or output from the first device.

A method of making a package is disclosed. The method may include forming bond pads on a first surface of a substrate, forming leads in the substrate by etching recesses in a second surface of the substrate, the second surface being opposite the first surface, and plating at least a portion of a top surface of the leads with a layer of finish plating. The method may also include thermosonically bonding the leads to a die by thermosonically bonding the finish plating to the die and encapsulating the die and the leads in an encapsulant.

A method for producing a power semiconductor module arrangement having a base plate and a contact element configured to, when the base plate is arranged in a housing, provide an electrical connection between an inside and an outside of the housing, includes: connecting an electrically insulating first layer to the base plate; and connecting the contact element to the first layer. Connecting the first layer to the base plate includes forming a third layer on the base plate or on the first layer and mounting the first layer on the base plate such that the third layer attaches the first layer to the base plate. Connecting the contact element to the first layer includes forming a second layer on the first layer or on the contact element and mounting the contact element on the first layer such that the second layer attaches the contact element to the first layer.

This power semiconductor device is provided with: a substrate; and a semiconductor element which is bonded onto the substrate using a sinterable metal bonding material. The semiconductor element comprises: a base; a first conductive layer that is provided on a first surface of the base, said first surface being on the substrate side; and a second conductive layer that is provided on a second surface of the base, said second surface being on the reverse side of the first surface. The thickness of the first conductive layer is from 0.5 times to 2.0 times (inclusive) the thickness of the second conductive layer.