A semiconductor device has an electrical component and a first TIM with a first compliant property is disposed over a surface of the electrical component. A second TIM having a second compliant property greater than the first compliant property is disposed over the surface of the electrical component within the first TIM. A third TIM can be disposed over the surface of the electrical component along the first TIM. A heat sink is disposed over the first TIM and second TIM. The second TIM has a shape of a star pattern, grid of dots, parallel lines, serpentine, or concentric geometric shapes. The first TIM provides adhesion for joint reliability and the second TIM provides stress relief. Alternatively, a heat spreader is disposed over the first TIM and second TIM and a heat sink is disposed over a third TIM and fourth TIM on the heat spreader.

Embodiments include a reflowable grid array (RGA) interposer, a semiconductor packaged system, and a method of forming the semiconductor packaged system. The RGA interposer includes a substrate having vias and zones, where the zones have embedded heaters. The heaters may include first traces, second traces, and via filament interconnects. The vias may have a z-height greater than a z-height of the heaters, and each of the zones may have a grid pattern. The RGA interposer may include first and second layers in the substrate, where the first layer includes the first traces, the second layer includes the second traces, and the second layer is over the first layer. The grid pattern may have parallel first traces orthogonal to parallel second traces to form a pattern of squares, where the pattern of squares has the first traces intersect the second traces substantially at right angles.

In the case where as a communication means among two or more control circuit boards corresponding to an on-vehicle environment, a wire harness is mounted, space-saving efficiency and assembly efficiency pose problems. When a board-to-board connector is utilized, arrangement of the control circuit boards cannot freely be performed, due to restriction of predetermined specific dimensions. An electric-power conversion apparatus includes a cooling device having a first surface, a second surface opposite to the first surface, and a hole penetrating the first surface and the second surface, a first control circuit board provided at the first surface side, a second control circuit board provided at the second surface side, and a pin header having a mold portion that partially wraps a connection pin penetrating the hole so as to connect the first control circuit board with the second control circuit board and that is fixed to the cooling device.

A method of manufacturing a cooling element, including: providing at least one first metal layer and at least one second metal layer, oxidizing the at least one first metal layer and/or the at least one second metal layer, structuring the at least one first metal layer and/or the at least one second metal layer to form at least one recess, joining the at least one first metal layer and the at least one second metal layer to form the cooling element, wherein, in the joined state, at least a partial section of a cooling channel in the cooling element is formed by the recess in the at least one first metal layer and/or the at least one second metal layer, and wherein, prior to the joining, an inner side of the recess is provided at least in sections free of an oxidized surface.

A semiconductor package includes: an insulating substrate; a first semiconductor chip; a second semiconductor chip with a thickness smaller than a thickness of the first semiconductor chip; a heat radiation member in which a main surface located on an opposite side of an active surface of the first semiconductor chip and an active surface of the second semiconductor chip, respectively, are bonded to a lower surface; and a sealing resin having contact with at least part of a side wall of the heat radiation member without being raised over an upper surface of the heat radiation member to seal the first and second semiconductor chips on the insulating substrate, wherein in the heat radiation member, a thickness of a first bonding part to which the first semiconductor chip is bonded is smaller than a thickness of a second bonding part to which the second semiconductor chip is bonded.

A method for producing a power semiconductor system includes packaging a power device in plastic to form a power semiconductor component, forming a first heat dissipation face on a surface of the power semiconductor component; heating a first material between a first heat sink and the first heat dissipation face; and cooling the first material on the first heat dissipation face to connect the power semiconductor component and the first heat sink.

Implementations of a semiconductor package may include one or more semiconductor die embedded in a substrate; at least three pin fin terminals coupled to the substrate; at least one signal lead connector and a fixture portion coupled to the substrate; and a coating directly coupled to all surfaces of the substrate exposed to a coolant during operation. The fixture portion may be configured to be fastened to a fixture in an immersion cooling enclosure that may include the coolant.

Implementations of a semiconductor package may include one or more semiconductor die directly coupled to only a direct leadframe attach (DLA) leadframe including two or more leads; and a coating covering the one or more semiconductor die and the DLA leadframe where when the semiconductor package is coupled into an immersion cooling enclosure, the coating may be in contact with a dielectric coolant while the two or more leads extend out of the immersion cooling enclosure.

An intelligent power module includes: an encapsulating material structure; a lead frame which is at least partially encapsulated inside the encapsulating material structure, wherein all portions of the lead frame encapsulated inside the encapsulating material structure are at a same planar level; and a heat dissipation structure, which is connected to the lead frame.

Embodiments disclosed herein include package substrates and methods of forming such package substrates. In an embodiment a package substrate comprises a core with a first surface and a second surface opposite from the first surface. In an embodiment, a buildup layer is over the first surface of the core. In an embodiment, a channel is through the core, where the channel extends in a direction that is substantially parallel to the first surface.