An electronic device structure having a shielding structure includes a substrate with an electronic component electrically connected to the substrate. The shielding structure includes conductive spaced-apart pillar structures that have proximate ends connected to the substrate and distal ends spaced apart from the substrate, and that are laterally spaced apart from the first electronic component. In one embodiment, the conductive pillar structures are conductive wires attached at one end to the substrate with an opposing end extending away from the substrate so that the conductive wires are provided generally perpendicular to the substrate. A package body encapsulates the electronic component and the conductive spaced-apart pillar structures. In one embodiment, the shielding structure further includes a shielding layer disposed adjacent the package body, which is electrically connected to the conductive spaced-apart pillar structures. In one embodiment, the electrical connection is made through the package. In another embodiment, the electrical connection is made through the substrate.

A method for preparing fan-out antenna packaging structure, includes: providing a carrier and a release layer structure; forming a single-layer antenna structure and a redistribution layer on an upper surface of the release layer; disposing a semiconductor chip electrically connected with the redistribution layer; forming a leading-out conducting wire on the redistribution layer at least on one side of the semiconductor chip; forming a plastic packaging layer wrapping the chip and the leading-out conducting wire; removing part of the plastic packaging layer to expose the chip and the leading-out conducting wire; forming an under-bump metal layer and a solder ball bump on an upper surface of the plastic packaging layer; removing the carrier and the release layer to expose the single-layer antenna structure; soldering a substrate on the solder ball bump; and forming a layer of cooling fins on a second surface of the semiconductor chip.

The present disclosure provides a method of fabricating an integrated fan-out package including the following steps. A semiconductor die is laterally encapsulated by an insulating encapsulant. A redistribution circuit structure is formed on the insulating encapsulant and the semiconductor die, and the redistribution circuit structure is electrically connected to the semiconductor die. A forming method of the redistribution circuit structure includes the following steps. A conductive wiring is formed over the insulating encapsulant and the semiconductor die. A dielectric material is formed on the insulating encapsulant and the semiconductor die to cover the conductive wiring. A sacrificial layer is formed on the dielectric material, wherein a first top surface of the sacrificial layer is flatter than a second top surface of the dielectric material. The sacrificial layer and a portion of the dielectric material are removed until the conductive wiring is revealed to form a dielectric layer, wherein the conductive wiring is embedded in the dielectric layer.

A semiconductor and a method of fabricating the semiconductor having multiple, interconnected die including: providing a semiconductor substrate having a plurality of disparate die formed within the semiconductor substrate, and a plurality of scribe lines formed between pairs of adjacent die of the plurality of disparate die; and fabricating, by a lithography system, a plurality of inter-die connections that extend between adjacent pair of die of the plurality of die.

The present disclosure provides a semiconductor IC structure having vertical wire bonding and method of making it. The method includes two steps. First step: providing a semiconductor chip, disposing a first solder joint and a second solder joint separately on its surface, disposing a wire bonding pad at the first solder joint, to connect to an internal functioning device of the semiconductor chip, and disposing a dummy pad at the second solder joint. Second step: bonding a metal wire on the wire bonding pad, cutting the metal wire on the dummy pad, and breaking the metal wire by pulling above the wire bonding pad, to obtain a vertical conductive column connected to the wire bonding pad.

A semiconductor memory device includes: a column of segments, each segment including bit cells; a local write bit (LWB) line; a local write bit_bar (LWB_bar) line; a global write bit (GWB) line; a global write bit_bar (GWBL_bar) line; each of the bit cells being connected correspondingly between the LWB and LWB_bar lines; and a distributed write driving arrangement including a global write driver connected between the GWB line and the LWB line and between the GWB_bar line and the LWB_bar line; and a local write driver included in each segment, each local write driver being connected between the GWB line and the LWB line and between the GWB_bar line and the LWB_bar line; and wherein: the global write driver and each local write driver is connected between the GWB line and the LWB line and between the GWB_bar line and the LWB_bar line.

A semiconductor device includes: a circuit unit including a semiconductor chip; a plurality of pin terminals formed in a rod shape extending in a same direction from the circuit unit and electrically connected to the circuit unit; a sealing resin portion sealing the circuit unit and first portions of the plurality of pin terminals positioned on a side of the circuit unit; and a plurality of covering resin portions integrally extending from an outer surface of the sealing resin portion from which second portions of the plurality of pin terminals protrude, the plurality of covering resin portions being formed in a cylindrical shape respectively covering base end portions of the second portions of the plurality of pin terminals, which are positioned on a side of the sealing resin portion.

An electronics package includes an insulating substrate, an electrical component having a back surface coupled to a first surface of the insulating substrate, and an insulating structure surrounding at least a portion of a perimeter of the electrical component. A first wiring layer extends from the first surface of the insulating substrate and over a sloped side surface of the insulating structure to electrically couple with at least one contact pad on an active surface of the electrical component. A second wiring layer is formed on a second surface of the insulating substrate and extends through at least one via therein to electrically couple with the first wiring layer.

An electronics package includes an insulating substrate, an electrical component having an active surface coupled to a first surface of the insulating substrate, and an insulating structure disposed adjacent the electrical component on the first surface of the insulating substrate. A first wiring layer is formed on a top surface of the insulating structure and extends down at least one sloped side surface of the insulating structure. A second wiring layer is formed on a second surface of the insulating substrate. The second wiring layer extends through a plurality of vias in the insulating substrate to electrically couple at least one contact pad on the active surface of the electrical component to the first wiring layer.

Techniques are disclosed herein for creating over and under interconnects. Using techniques described herein, over and under interconnects are created on an IC. Instead of creating signaling interconnects and power/ground interconnects on a same side of a chip assembly, the signaling interconnects can be placed on an opposing side of the chip assembly as compared to the power interconnects.