A system and method for connecting semiconductor dies is provided. An embodiment comprises connecting a first semiconductor die with a first width to a second semiconductor die with a larger second width and that is still connected to a semiconductor wafer. The first semiconductor die is encapsulated after it is connected, and the encapsulant and first semiconductor die are thinned to expose a through substrate via within the first semiconductor die. The second semiconductor die is singulated from the semiconductor wafer, and the combined first semiconductor die and second semiconductor die are then connected to another substrate.

A semiconductor package includes a semiconductor die having a first surface and a second surface opposite to the first surface, a conductive wiring layer stacked with the semiconductor die and proximal to the first surface, an encapsulant encapsulating the semiconductor die and stacked with the conductive wiring layer, and a replacement structure exposing from the encapsulant and being free of fillers. A method for manufacturing the semiconductor package is also disclosed in the present disclosure.

The present invention provides a packaging method and a packaging device for selectively encapsulating a packaging structure. The method includes: providing a substrate; mounting components on the substrate, the components including a component that needs to be encapsulated and a component that does not need to be encapsulated; forming a protective structure in an area of the component that does not need to be encapsulated so as to form a protective area for isolating the component that does not need to be encapsulated and an encapsulating area located outside the protective area; filling the encapsulating area with an injection molding material; and removing the protective structure. According to the present invention, any part of the packaging structure may be selectively encapsulated by self-adjustment as required. The operation is simple, and the process flow is simplified.

A die package includes a semiconductor die, a passive component, a molding compound and a redistribution layer (RDL). The semiconductor die includes a first bonding pad. The passive component includes a second bonding pad. The molding compound encloses the semiconductor die and the passive component. The RDL is disposed over the semiconductor die and the passive component and electrically connecting the first bonding pad with the second bonding pad. The semiconductor die is vertically overlapped with the passive component.

A method includes forming a release film over a carrier, attaching a device over the release film through a die-attach film, encapsulating the device in an encapsulating material, performing a planarization on the encapsulating material to expose the device, detaching the device and the encapsulating material from the carrier, etching the die-attach film to expose a back surface of the device, and applying a thermal conductive material on the back surface of the device.

A semiconductor package including a semiconductor chip, an interposer on the semiconductor chip, and a molding layer covering at least a portion of the semiconductor chip and at least a portion of the interposer may be provided. The interposer includes a interposer substrate and a heat dissipation pattern penetrating the interposer substrate and electrically insulated from the semiconductor chip. The heat dissipation pattern includes a through electrode disposed in the interposer substrate and an upper pad disposed on an upper surface of the interposer substrate and connected to the through electrode. The molding layer covers at least a portion of a sidewall of the upper pad and the upper surface of the interposer substrate. At least a portion of an upper surface of the upper pad is not covered by the molding layer.

A release film may include a conductive polymer substrate layer, and release layers provided on a top surface and a bottom surface of the conductive polymer substrate layer. Each of the release layers may include a fluorine-based polymer, and a density of the conductive polymer substrate layer ranges from 0.1 g/cm.sup.3 to 0.5 g/cm.sup.3.

Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a spacer material on an encapsulant such that the encapsulant separates the spacer material from an active surface of a semiconductor device and at least one interconnect projecting away from the active surface. The method further includes molding the encapsulant such that at least a portion of the interconnect extends through the encapsulant and into the spacer material. The interconnect can include a contact surface that is substantially co-planar with the active surface of the semiconductor device for providing an electrical connection with the semiconductor device.

A semiconductor package structure includes a conductive structure, at least one semiconductor element, an encapsulant, a redistribution structure and a plurality of bonding wires. The semiconductor element is disposed on and electrically connected to the conductive structure. The encapsulant is disposed on the conductive structure to cover the semiconductor element. The redistribution structure is disposed on the encapsulant, and includes a redistribution layer. The bonding wires electrically connect the redistribution structure and the conductive structure.

A laminate including a glass plate and a coating layer, wherein the coating layer includes one or more components selected from the group consisting of silicon nitride, titanium oxide, alumina, niobium oxide, zirconia, indium tin oxide, silicon oxide, magnesium fluoride, and calcium fluoride, wherein a ratio (dc/dg) of a thickness dc of the coating layer to a thickness dg of the glass plate is in a range of 0.05×10.sup.−3 to 1.2×10.sup.−3, and wherein a radius of curvature r1 of the laminate with negating of self-weight deflection is 10 m to 150 m.