Package structures and methods of forming the same are disclosed. A package structure includes a die, a molding member and a redistribution circuit structure. The die includes a semiconductor substrate, a connector and a passivation layer. The semiconductor substrate has a top surface. The connector is disposed over the top surface of the semiconductor substrate. The passivation layer is disposed over the top surface of the semiconductor substrate and exposes a portion of the connector. The molding member laterally surrounds the semiconductor substrate, wherein a top surface of the molding member is higher than the top surface of the semiconductor substrate and the molding member forms a hooking structure that embraces over an edge portion of the semiconductor substrate. The redistribution circuit structure extends over the passivation layer and the molding member, and is electrically connected to the connector.

This disclosure provides a package substrate fabrication method including: forming a first conductive wire and a first connecting unit on a first carrier substrate; forming a first dielectric layer on the first carrier substrate while enabling an end face of the first connecting unit to be exposed; bonding a second carrier substrate to the first dielectric layer and removing the first carrier substrate; disposing a first circuit chip and a second connecting unit on the first conductive wire; forming a second dielectric layer on the second carrier substrate while enabling the first circuit chip and the second connecting unit to be surrounded by the second dielectric layer and an end face of the second connecting unit to be exposed; forming a second conductive wire on the second dielectric layer; disposing a second circuit chip on the second conductive wire; and forming a third dielectric layer on the second carrier substrate.

A package structure includes at least one semiconductor die, an insulating encapsulant, an isolation layer and a redistribution layer. The at least one first semiconductor die has a semiconductor substrate and a conductive post disposed on the semiconductor substrate. The insulating encapsulant is partially encapsulating the first semiconductor die, wherein the conductive post has a first portion surrounded by the insulating encapsulant and a second portion that protrudes out from the insulating encapsulant. The isolation layer is disposed on the insulating encapsulant and surrounding the second portion of the conductive post. The redistribution layer is disposed on the first semiconductor die and the isolation layer, wherein the redistribution layer is electrically connected to the conductive post of the first semiconductor die.

A method of forming a package assembly includes forming a no-flow underfill layer on a substrate. The method further includes attaching a semiconductor die to the substrate. The semiconductor die comprises a bump and a molding compound layer in physical contact with a lower portion of the bump. An upper portion of the bump is in physical contact with the no-flow underfill layer.

[Problem] To provide a multi-layer sheet for mold underfill encapsulation, which exhibits good infiltrability between electrodes. [Solution] In order to solve the aforementioned problem, the present invention provides a multi-layer sheet for mold underfill encapsulation, which is characterized by having provided as an outermost layer thereof an (A) layer that comprises a resin composition having a local maximum loss tangent (tan δ) value of 3 or more at a measurement temperature of 125° C. for a measurement time of 0-100 seconds.

A method for manufacturing a semiconductor device includes providing a wafer that includes a device region and a peripheral region of the device region, the device region including multiple chip regions. The method includes removing a portion of the peripheral region such that the removed portion has an annular shape. The method includes forming a protective layer on a first surface of the wafer. The method includes grinding a second surface of the wafer in which the protective layer is formed on the first surface.

Packaged semiconductor devices including high-thermal conductivity molding compounds and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first redistribution structure; a first die over and electrically coupled to the first redistribution structure; a first through via over and electrically coupled to the first redistribution structure; an insulation layer extending along the first redistribution structure, the first die, and the first through via; and an encapsulant over the insulation layer, the encapsulant surrounding portions of the first through via and the first die, the encapsulant including conductive fillers at a concentration ranging from 70% to about 95% by volume.

A device package includes a sensor die, one or more additional dies adjacent the sensor die, and a molding compound encircling the sensor die and the one or more additional dies. The device package further includes redistribution layers over the sensor die, the one or more additional dies, and the molding compound. The redistribution layers include first conductive features in a first dielectric layer. The first conductive features electrically connect the sensor die to the one or more additional dies. The redistribution layers further include an array of electrodes in a second dielectric layer over the first dielectric layer and electrically connected to the sensor die.

A method includes followings operations. A substrate including a first surface and a second surface is provided. The substrate and a transparent film are heated to attach the transparent film on the first surface. A first coefficient of a thermal expansion (CTE) mismatch is between the substrate and the transparent film. The substrate and the transparent film are cooled. A polymeric material is disposed on the second surface. A second CTE mismatch is between the substrate and the polymeric material. The second CTE mismatch is counteracted by the first CTE mismatch.

Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a spacer material on an encapsulant such that the encapsulant separates the spacer material from an active surface of a semiconductor device and at least one interconnect projecting away from the active surface. The method further includes molding the encapsulant such that at least a portion of the interconnect extends through the encapsulant and into the spacer material. The interconnect can include a contact surface that is substantially co-planar with the active surface of the semiconductor device for providing an electrical connection with the semiconductor device.