A semiconductor device, includes: a semiconductor element including an element main surface and an element back surface facing opposite sides in a thickness direction; a wiring part electrically connected to the semiconductor element; an electrode pad electrically connected to the wiring part; a sealing resin configured to cover a part of the semiconductor element; and a first metal layer configured to make contact with the element back surface and exposed from the sealing resin, wherein the semiconductor element overlaps the first metal layer when viewed in the thickness direction.

Semiconductor devices are provided in which a first semiconductor device is bonded to a second semiconductor device. The bonding may occur at a gate level, a gate contact level, a first metallization layer, a middle metallization layer, or a top metallization layer of either the first semiconductor device or the second semiconductor device.

A semiconductor package includes a substrate, a first and a second semiconductor die arranged on the substrate, a molded body encapsulating the first and second semiconductor dies, the molded body including a first external side facing away from the substrate, a plurality of electrical connectors extending at least partially through the molded body from the first external side to the first and/or second semiconductor die, and a plurality of plated conductive tracks arranged in trenches within the molded body on the first external side. T conductive tracks are coupled to the first and/or second semiconductor die by the electrical connectors.

In a frame member including a first region and a second region that are extending in a first direction in parallel to each other while being spaced apart from each other, first and second plating films are formed in the first and second regions, respectively. The second plating film is different in a type from the first plating film. Then, a stamping process is performed to the frame member including the first region and the second region, thereby a lead frame including a plurality of leads is formed. The lead frame includes a first lead group and a second lead group. The first plating film is formed in the first lead group, but the second plating film is not formed in the first lead group. Meanwhile, the second plating film is formed in the second lead group, but the first plating film is not formed in the second lead group.

A semiconductor package includes a die pad and leads extending from the die pad. Each lead has a free end with outer surfaces extending at angles from one another. An electrically conductive plating material covers at least portions of the outer surfaces. A die attached to the die pad is electrically connected to the leads. An insulating layer extends over the leads and the die such that the free ends of the leads are exposed.

Semiconductor devices are provided in which a first semiconductor device is bonded to a second semiconductor device. The bonding may occur at a gate level, a gate contact level, a first metallization layer, a middle metallization layer, or a top metallization layer of either the first semiconductor device or the second semiconductor device.

An electronic component includes a lead frame; a semiconductor chip arranged above the lead frame; and a connection layer sequence arranged between the lead frame and the semiconductor chip, wherein the connection layer sequence includes a first intermetallic layer including gold and indium or gold, indium and tin, a second intermetallic layer including indium and a titanium compound, indium and nickel, indium and platinum or indium and titanium, and a third intermetallic layer including indium and gold.

A leadless package with wettable flanks is formed by providing a substrate and plating a metal layer onto the substrate to form a contact on the substrate extending across a saw street. An encapsulant is deposited over the contact. The substrate is removed to expose the contact and encapsulant. The encapsulant and contact are singulated. In some embodiments, the substrate includes a ridge, and the contact is formed over the ridge.

A method can include coupling a semiconductor chip and an electrode with a substrate. Bottom and top mold die can be use, where the top mold die define a first space and a second space that is separated from the first space. The method can include injecting encapsulation material to form an encapsulation member coupled to and covering at least a portion of the substrate. The encapsulation member can include a housing unit housing the electrode. The electrode can have a conductive sidewall exposed to, and not in contact with the encapsulation member, such that there is open space between the conductive sidewall of the electrode and the encapsulation member from an uppermost surface to a bottommost surface of the encapsulation member, the substrate can having a portion exposed within the open space, and the encapsulation member can have an open cross-section perpendicular to an upper surface of the substrate.

A method of attaching a semiconductor chip on a lead frame includes A) providing a semiconductor chip, B) applying a solder metal layer sequence to the semiconductor chip, wherein the solder metal layer sequence includes a first metallic layer including indium or an indium-tin alloy, C) providing a lead frame, D) applying a metallization layer sequence to the lead frame, wherein the metallization layer sequence includes a fourth layer including indium and/or tin arranged above the lead frame and a third layer including gold arranged above the fourth layer, E) forming an intermetallic intermediate layer including gold and indium, gold and tin or gold, tin and indium, G) applying the semiconductor chip to the lead frame via the solder metal layer sequence and the intermetallic intermediate layer, and H) heating the arrangement produced in G) to attach the semiconductor chip to the lead frame.