A cover for an integrated circuit package includes a central plate and a peripheral frame surrounding the central plate. The peripheral frame is vertically spaced from and parallel to the central plate. The peripheral frame includes through openings formed therein. The cover can be used to package a semiconductor chip that is mounted to a substrate.

A semiconductor module includes a laminated substrate having an insulating plate, a circuit pattern arranged on an upper surface of the insulating plate and a heat dissipating plate arranged on a lower surface of the insulating plate. The semiconductor module also includes a semiconductor device having a collector electrode arranged on its upper surface, having an emitter electrode and a gate electrode arranged on its lower surface, and bumps respectively bonding the emitter electrode and the gate electrode to an upper surface of the circuit pattern. Each of the bumps is made of a metal sintered material such that the bump is formed to be constricted in its middle portion in a thickness direction orthogonal to a surface of the insulating plate.

Certain aspects of the present disclosure generally relate to a chip package having through-package partial vias. An example chip package generally includes a first substrate, a second substrate, an integrated circuit die, and one or more conductive vias. The integrated circuit die is disposed between the first substrate and the second substrate. The one or more conductive vias are disposed on at least one edge of at least one of the first substrate or the second substrate and electrically coupled to at least one of the first substrate or the second substrate.

An integrated shield electronic component package includes a substrate having an upper surface, a lower surface, and sides extending between the upper surface and the lower surface. An electronic component is mounted to the upper surface of the substrate. An integrated shield is mounted to the upper surface of the substrate and includes a side shielding portion directly adjacent to and covering the sides of the substrate. The integrated shield covers and provides an electromagnetic interference (EMI) shield for the electronic component, the upper surface and sides of substrate. Further, the integrated shield is integrated within the integrated shield electronic package. Thus, separate operations of mounting an electronic component package and then mounting a shield are avoided thus simplifying manufacturing and reducing overall assembly costs.

An integrated shield electronic component package includes a substrate having an upper surface, a lower surface, and sides extending between the upper surface and the lower surface. An electronic component is mounted to the upper surface of the substrate. An integrated shield is mounted to the upper surface of the substrate and includes a side shielding portion directly adjacent to and covering the sides of the substrate. The integrated shield covers and provides an electromagnetic interference (EMI) shield for the electronic component, the upper surface and sides of substrate. Further, the integrated shield is integrated within the integrated shield electronic package. Thus, separate operations of mounting an electronic component package and then mounting a shield are avoided thus simplifying manufacturing and reducing overall assembly costs.

A semiconductor package includes a semiconductor chip disposed over a first main surface of a first substrate, a package lid disposed over the semiconductor chip, and spacers extending from the package lid through corresponding holes in the first substrate. The spacers enter the holes at a first main surface of the first substrate and extend beyond an opposing second main surface of the first substrate.

Disclosed embodiments include multi-level fan-out integrated-circuit package substrates that provide a low-loss path to active and passive devices, by shunting away from interconnects and inductive loops. The multi-level form factor of a molded mass, allows for the low-loss path.

Electronic packages and methods of formation are described in which an interposer is solderlessly connected with a package substrate. In an embodiment, the interposer is stacked on the package substrate and joined with a conductive film. In an embodiment the interposer is formed on the package substrate during a reconstitution sequence.

A device includes a polymer. A device die is disposed in the polymer. A passive device includes three Through Assembly Vias (TAVs) penetrating through the polymer, wherein the TAVs are coupled in series. A Redistribution Line (RDL) is underlying the polymer. The RDL electrically couples a first one of the TAVs to a second one of the TAVs.

A device includes a polymer. A device die is disposed in the polymer. A passive device includes three Through Assembly Vias (TAVs) penetrating through the polymer, wherein the TAVs are coupled in series. A Redistribution Line (RDL) is underlying the polymer. The RDL electrically couples a first one of the TAVs to a second one of the TAVs.