The present disclosure discloses a method for preparing an isolation area of a gallium oxide device, the method comprising: depositing a mask layer on a gallium oxide material; removing a preset portion region of the mask layer; preparing an isolation area in a position, corresponding to the preset portion region, on the gallium oxide material by using a high-temperature oxidation technique, with the isolation area being located between active areas of the gallium oxide device; and removing the remaining mask layer on the gallium oxide material. In the disclosure, the isolation area is prepared by using the high-temperature oxidation technique, which prevents damage to the gallium oxide device during the preparation of the isolation area, thereby achieving isolation between the active areas of the gallium oxide device.

There is disclosed a substrate processing method for etching a substrate on which a first and a second silicon oxide layer having different film qualities are formed side by side. The substrate processing method includes: a first etching step of supplying a halogen-containing gas that is not activated to the substrate and sublimating reaction by-products generated by reaction between the halogen-containing gas and the first and the second silicon oxide layer; and a second etching step of etching the substrate by radicals generated by activating the halogen-containing gas.

A method of manufacturing a reverse-blocking IGBT (insulated gate bipolar transistor) includes forming a plurality of IGBT cells in a device region of a semiconductor substrate, forming a reverse-blocking edge termination structure in a periphery region of the semiconductor substrate which surrounds the device region, etching one or more trenches in the periphery region between the reverse-blocking edge termination structure and a kerf region of the semiconductor substrate, depositing a p-type dopant source which at least partly fills the one or more trenches and diffusing p-type dopants from the p-type dopant source into semiconductor material surrounding the one or more trenches, so as to form a continuous p-type doped region in the periphery region which extends from a top surface of the semiconductor substrate to a bottom surface of the semiconductor substrate after thinning of the semiconductor substrate at the bottom surface.

A gate controlled semiconductor device comprising a collector region of a first conductivity type; a drift region of a second conductivity type located over the collector region; a body region of a first conductivity type located over the drift region; at least one first contact region of a second conductivity type located above the body region and having a higher doping concentration compared to the body region. The device further comprises at least one second contact region of a first conductivity type located laterally adjacent to the at least one first contact region, the at least one second contact region having a higher doping concentration than the body region. The device further comprises at least one active trench extending from a surface into the drift region, in which the at least one first contact region adjoins the at least one active trench so that, in use, a channel region is formed along said at least one active trench and within the body region. The at least one active trench comprises: two vertical sidewalls and a bottom surface between the two vertical sidewalls; and an insulation layer along the vertical side walls and the bottom surface, wherein the insulation layer along at least one vertical side wall comprises different thicknesses; at least one auxiliary trench extending from the surface into the drift region. The at least one auxiliary trench comprises: two vertical sidewalls and a bottom surface between the two vertical sidewalls; and an insulation layer along the vertical side walls and the bottom surface, wherein the insulation layer along at least one vertical side wall comprises a constant thickness.

A display device includes: a substrate that includes an opening and a display area that surrounds the opening; a plurality of grooves formed in the substrate between the opening and the display area; a display element layer on the substrate and that includes a plurality of display elements in the display area; a thin-film encapsulation layer disposed on the display element layer, the thin-film encapsulation layer including a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer which are sequentially stacked; a planarization layer disposed over the plurality of grooves and that includes an organic insulating material, wherein the planarization layer is disposed over the second inorganic encapsulation layer, and the organic encapsulation layer is disposed below the second inorganic encapsulation layer.

Provided is a semiconductor device including a substrate having a first conductivity type; an isolation structure disposed in the substrate to form an active region in the substrate; a well region having the first conductivity type, extending from an inner sidewall of the isolation structure into the active region, wherein a portion of the substrate is surrounded by the well region to form a native region in the active region; a gate structure disposed over the active region; and doped regions having a second conductivity type, disposed respectively in the active region at two sides of the gate structure, wherein a portion of the native region is sandwiched between the doped regions to form a channel region below the gate structure, and a doping concentration of the channel region is substantially equal to a doping concentration of the substrate.

A process for producing a donor substrate for creating a three-dimensional integrated structure comprises the following steps: providing a semiconductor substrate comprising a surface layer, referred to as an active layer, and a layer comprising a plurality of cavities extending beneath the active layer, each cavity being separated from an adjacent cavity by a partition, forming an electronic device in a region of the active layer located plumb with a cavity, depositing a protective mask on the active layer so as to cover the electronic device while at the same time exposing a region of the active layer located plumb with each partition, and implanting atomic species through regions of the active layer exposed by the mask to form a weakened zone in each partition.

In an embodiment, a method of forming a semiconductor may include forming a plurality of active trenches and forming a termination trench substantially surrounding an outer periphery of the plurality of active trenches. The method may also include forming at least one active trench of the plurality of active trenches having corners linking trench ends to sides of active trenches wherein each active trench of the plurality of active trenches has a first profile along the first length and a second profile at or near the trench ends; and forming a termination trench substantially surrounding an outer periphery of the plurality of active trenches and having a second profile wherein one of the first profile or the second profile includes a non-linear shape.

A lighted assembly includes a perforated member having a plurality of relatively small openings therethrough. The openings are arranged to provide areas forming letters, designs, or the like. A light source may be positioned adjacent the perforated member whereby light from the light source travels through the openings to form illuminated letters, designs or the like. The perforations may be filled with a light-transmitting polymer material. The light source may comprise an LED and a light guide that distributes light along a lower side of the perforated member. The light source may be positioned in a waterproof housing that is sealed to the perforated member.

A method for making a deep trench isolation of a CIS device includes: growing a first epitaxial layer on a substrate; forming a hard mask layer on the first epitaxial layer; performing photolithography and etching processes to form deep trenches arranged longitudinally and transversely in the first epitaxial layer; forming a second epitaxial layer in the deep trenches; performing a thermal oxidation process to form a first oxide layer on the surface of the second epitaxial layer; completely filling the deep trenches with polysilicon; performing a back-etching process to expose sidewalls of the first oxide layer in the deep trenches; forming a second oxide layer on the top of the polysilicon; removing the hard mask layer and the first oxide layer above the second oxide layer; rapidly growing a third epitaxial layer; and performing a CMP process to form a deep trench isolation on the substrate.