An integrated circuit may be formed by forming an isolation recess in a single-crystal silicon-based substrate. Sidewall insulators are formed on sidewalls of the isolation recess. Thermal oxide is formed at a bottom surface of the isolation recess to provide a buried isolation layer, which does not extend up the sidewall insulators. A single-crystal silicon-based semiconductor layer is formed over the buried isolation layer and planarized to be substantially coplanar with the substrate adjacent to the isolation recess, thus forming an isolated semiconductor layer over the buried isolation layer. The isolated semiconductor layer is laterally separated from the substrate.

A method and structure of forming air gaps with a sidewall image transfer process such as self-aligned double patterning to reduce capacitances. Different materials can be provided in the mandrel and non-mandrel regions to enlarge a process window for metal line end formation.

Techniques are disclosed for controlling transistor sub-fin leakage. The techniques can be used for highly scaled finFETs, as well as other non-planar transistors. In some cases, the techniques include exposing a middle portion of a fin structure formed on a substrate and then converting the exposed portion to an electrically isolating material via a doping or oxidation process. For example, a monolayer doping (MLD) process may be used to deliver dopants to the exposed portion of the fin in a self-saturated monolayer scheme. In another example case, thermal oxidation may be used to convert the exposed portion to an insulator material. In some cases, a barrier layer (e.g., including carbon doping) may be located above the exposed portion of the fin to help prevent the doping or oxidation process from affecting the upper region of the fin, which is used for the transistor channel.

A display device includes: a substrate that includes an opening and a display area that surrounds the opening; a plurality of grooves formed in the substrate between the opening and the display area; a display element layer on the substrate and that includes a plurality of display elements in the display area; a thin-film encapsulation layer disposed on the display element layer, the thin-film encapsulation layer including a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer which are sequentially stacked; a planarization layer disposed over the plurality of grooves and that includes an organic insulating material, wherein the planarization layer is disposed over the second inorganic encapsulation layer, and the organic encapsulation layer is disposed below the second inorganic encapsulation layer.

The present invention provides a nitride semiconductor device capable of forming a half-bridge circuit and suppressing changes in current collapse characteristics.

A first transistor of the present invention includes a first nitride semiconductor layer, and a first gate electrode, a first source electrode and a first drain electrode formed thereon. The second transistor includes a second nitride semiconductor layer, and a second gate electrode, a second source electrode and a second drain electrode formed thereon. The source electrode is electrically connected to a lower region of a first region on the substrate, the second source electrode is electrically connected to a lower region of a second region on the substrate, and a first insulating region is disposed between a portion corresponding to the first region on the substrate and a portion corresponding to the second region on the substrate.

Method of forming an electronic device with a bottom isolation dielectric between a pair of gate stacks is described. Each of the gate stacks comprises a plurality of gate layers. A sacrificial film having a liner on a top and side thereof is on top of the gate layers. A capping layer is on the top of the liner.

A method for forming a semiconductor structure is disclosed. Among a stack of mask layers, any other layers above the lowermost thin film layer are subsequently removed to expose the lowermost thin film layer and then the lowermost thin film layer is separately removed by a dry etching process. This improves an etching uniformity of the lowermost thin film layer and ameliorates the issue of material residues. Moreover, thanks to the anisotropic characteristic of the dry etching process, lateral etching of side walls of a trench isolation structure can be mitigated.

Methods, apparatuses, and systems related to forming a semiconductor using hybrid oxidation are described. An example method includes forming an opening to create an isolation region in a semiconductor substrate. The example method further includes depositing a first dielectric into the isolation region at a first oxidation rate. The example method further includes depositing a second dielectric into the isolation region at a second oxidation rate.

The disclosure provides a plane polishing method and a processing method of the silicon wafer. The plane polishing method includes steps of: depositing a hard mask on a silicon substrate to form a silicon wafer base material; forming an opening on the hard mask by photolithography or etching; carrying out an oxidation reaction on a portion of the silicon substrate exposed by the opening, forming an oxide layer having a bottom embedded in the silicon substrate and a top protruding and exposed outside the hard mask by oxidizing the silicon substrate; and polishing the oxide layer by chemical mechanical planarization. In the present disclosure, the surface formed by the oxide layer and the hard mask flat is flat, without a recess even in the case of large structures, thereby precisely controlling a shape and a depth of the cavity in accordance with an oxidation rate on a silicon substrate.

A semiconductor device includes a substrate having a semiconductor layer. A trench is formed within the semiconductor layer. A filling insulating film is disposed within the trench. An insertion liner is disposed within the filling insulating film. The insertion liner is spaced apart from the semiconductor layer and extends along the bottom surface of the trench.