An integrated circuit (IC) structure includes an active device over a bulk semiconductor substrate, and an isolation structure around the active device in the bulk semiconductor substrate. The active device includes a semiconductor layer having a center region, a first end region laterally spaced from the center region by a first trench isolation, a second end region laterally spaced from the center region by a second trench isolation, a gate over the center region, and a source/drain region in each of the first and second end regions. The isolation structure includes: a polycrystalline isolation layer under the active device, a third trench isolation around the active device, and a porous semiconductor layer between the first trench isolation and the polycrystalline isolation layer and between the second trench isolation and the polycrystalline isolation layer.

Generally, examples described herein relate to methods and processing systems for forming isolation structures (e.g., shallow trench isolations (STIs)) between fins on a substrate. In an example, fins are formed on a substrate. A liner layer is conformally formed on and between the fins. Forming the liner layer includes conformally depositing a pre-liner layer on and between the fins, and densifying, using a plasma treatment, the pre-liner layer to form the liner layer. A dielectric material is formed on the liner layer.

An embodiment includes a method including forming an opening in a cut metal gate region of a metal gate structure of a semiconductor device, conformally depositing a first dielectric layer in the opening, conformally depositing a silicon layer over the first dielectric layer, performing an oxidation process on the silicon layer to form a first silicon oxide layer, filling the opening with a second silicon oxide layer, performing a chemical mechanical polishing on the second silicon oxide layer and the first dielectric layer to form a cut metal gate plug, the chemical mechanical polishing exposing the metal gate structure of the semiconductor device, and forming a first contact to a first portion of the metal gate structure and a second contact to a second portion of the metal gate structure, the first portion and the second portion of the metal gate structure being separated by the cut metal gate plug.

A method of manufacturing a semiconductor structure includes: etching a substrate according to a hard mask to form a plurality of trenches in the substrate; performing a nitridation treatment on the trenches of the substrate; filling the trenches of the substrate with a flowable isolation material; and solidifying the flowable isolation material to form an isolation material. A semiconductor structure manufactured by the method is also provided.

A method includes depositing a first dielectric layer in an opening, the first dielectric layer comprising a semiconductor element and a non-semiconductor element. The method further includes depositing a semiconductor layer on the first dielectric layer, the semiconductor layer comprising a first element that is the same as the semiconductor element. The method further includes introducing a second element to the semiconductor layer wherein the second element is the same as the non-semiconductor element. The method further includes applying a thermal annealing process to the semiconductor layer to change the semiconductor layer into a second dielectric layer.

Methods for gapfill of high aspect ratio features are described. A first film is deposited on the bottom and upper sidewalls of a feature. The first film is etched from the sidewalls of the feature and the first film in the bottom of the feature is treated to form a second film. The deposition, etch and treat processes are repeated to fill the feature.

Methods of processing thin film by oxidation at high pressure are described. The methods are generally performed at pressures greater than 2 bar. The methods can be performed at lower temperatures and have shorter exposure times than similar methods performed at lower pressures. Some methods relate to oxidizing tungsten films to form self-aligned pillars.

Semiconductor-on-insulator (SOI) field effect transistors (FETs) including body regions having different thicknesses may be formed on an SOI substrate by selectively thinning a region of a top semiconductor layer while preventing thinning of an additional region of the top semiconductor layer. An oxidation process or an etch process may be used to thin the region of the top semiconductor layer, and a patterned oxidation barrier mask or an etch mask may be used to prevent oxidation or etching of the additional portion of the top semiconductor layer. Shallow trench isolation structures may be formed prior to, or after, the selective thinning processing steps. FETs having different depletion region configurations may be formed using the multiple thicknesses of the patterned portions of the top semiconductor layer. For example, partially depleted SOI FETs and fully depleted SOI FETs may be provided.

A method includes etching a semiconductor substrate to form a trench and a semiconductor strip. A sidewall of the semiconductor strip is exposed to the trench. The method further includes depositing a silicon-containing layer extending into the trench, wherein the silicon-containing layer extends on the sidewall of the semiconductor strip, filling the trench with a dielectric material, wherein the dielectric material is on a sidewall of the silicon-containing layer, and oxidizing the silicon-containing layer to form a liner. The liner comprises oxidized silicon. The liner and the dielectric material form parts of an isolation region. The isolation region is recessed, so that a portion of the semiconductor strip protrudes higher than a top surface of the isolation region forms a semiconductor fin.

Apparatuses and methods are disclosed. One such apparatus includes a well having a first type of conductivity formed within a semiconductor structure having a second type of conductivity. A boundary of the well has an edge that is substantially beneath an edge of an active area of a tap to the well.