A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.

The present disclosure provides a semiconductor structure having a fin structure. The semiconductor includes a substrate defined with an active region. A first gate structure is disposed in the active region and includes a dielectric material. A second gate structure is disposed in the active region and includes the dielectric material. A fin structure having a first top surface is arranged to alternate with the first gate structure and the second gate structure. The first gate structure has a second top surface and the second gate structure has a third top surface. The second top surface and the third top surface are lower than the first top surface.

Embodiments of the disclosure provide a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a substrate, a first isolation trench located in the substrate, a first insulating layer covering a bottom surface and a lower part of a sidewall of the first isolation trench, a second insulating layer covering an upper part of the sidewall of the first isolation trench, and a third insulating layer at least partially located between the first insulating layer and the second insulating layer to isolate the first insulating layer from the second insulating layer.

A semiconductor device includes a substrate having one or more inner surfaces defining trenches that define an active pattern of the substrate, the trenches including a first trench and a second trench which have different widths, a device isolation layer on the substrate such that the device isolation layer at least partially fills the trenches, and a word line intersecting the active pattern. The device isolation layer includes a first isolation pattern covering a portion of the second trench, a second isolation pattern on the first isolation pattern and covering a remaining portion of the second trench, and a filling pattern filling the first trench under the word line. A top surface of the second isolation pattern is located at a higher level than a top surface of the filling pattern.

A semiconductor structure having fins is provided. The semiconductor structure includes a semiconductor substrate and an isolation structure. The semiconductor substrate includes a first fin. The isolation structure defines the first fin. The isolation structure includes a first portion and a second portion on two opposite sides of the first fin. A difference between an elevation of a top surface of the first portion and an elevation of a top surface of the second portion is greater than 0 and less than about 5 nm.

Semiconductor devices and methods of forming the same are provided. The methods may implanting dopants into a substrate to form a preliminary impurity region and heating the substrate to convert the preliminary impurity region into an impurity region. Heating the substrate may be performed at an ambient temperature of from about 800° C. to about 950° C. for from about 20 min to about 50 min. The method may also include forming first and second trenches in the impurity region to define an active fin and forming a first isolation layer and a second isolation layer in the first and second trenches, respectively. The first and second isolation layers may expose opposing sides of the active fin. The method may further include forming a gate insulation layer extending on the opposing sides and an upper surface of the active fin and forming a gate electrode traversing the active fin.

A first FinFET device includes first fin structures that extend in a first direction in a top view. A second FinFET device includes second fin structures that extend in the first direction in the top view. The first FinFET device and the second FinFET device are different types of FinFET devices. A plurality of gate structures extend in a second direction in the top view. The second direction is different from the first direction. Each of the gate structures partially wraps around the first fin structures and the second fin structures. A dielectric structure is disposed between the first FinFET device and the second FinFET device. The dielectric structure cuts each of the gate structures into a first segment for the first FinFET device and a second segment for the second FinFET device. The dielectric structure is located closer to the first FinFET device than to the second FinFET device.

A method for fabricating a semiconductor device includes following steps: A patterned mask layer including a plurality of standing walls and a covering part is formed on a surface of a semiconductor substrate, wherein two adjacent standing walls define a first opening exposing a part of the surface, and the covering part blankets the surface. A first patterned photoresist layer is formed to partially cover the covering part. A first etching process is performed to form a first trench in the substrate, passing through the surface and aligning with the first opening. A portion of the patterned mask layer is removed to form a second opening exposing another portion of the surface. A second etching process is performed to form a second trench in the substrate and define an active area on the surface. The depth of the first trench is greater than that of the second trench.

A semiconductor device includes a semiconductor substrate, a gate dielectric, a gate electrode, and a pair of source/drain regions. The gate dielectric is disposed in the semiconductor substrate having an upper boundary lower than an upper surface of the semiconductor substrate, and an upper surface flush with the upper surface of the semiconductor substrate. The gate electrode is disposed over the gate dielectric having a first section over the upper boundary of the gate dielectric and a second section over the upper surface of the gate dielectric. The second section partially covers and partially exposes the upper surface of the gate dielectric. The pair of source/drain regions are disposed on opposing sides of the gate dielectric.

The present disclosure relates to a semiconductor device and a method of fabricating the same. The semiconductor device includes a substrate, an active structure, and a shallow trench isolation. The active structure is disposed in the substrate, and includes a plurality of first active fragments and a plurality of second active fragments, with the first active fragments and the second active fragments parallel and separately extended along a first direction. A plurality of first openings disposed in the substrate, between two adjacent ones of the first active fragments, and a plurality of second openings disposed in the substrate, between two adjacent ones of the second active fragments, wherein an aperture of the second openings is greater than an aperture of the first openings. The shallow trench isolation is disposed in the substrate to fill in the first openings and the second openings, and to surround the active structure.