A semiconductor device including a gate separation region is provided. The semiconductor device includes an isolation region between active regions; interlayer insulating layers on the isolation region; gate line structures overlapping the active regions, disposed on the isolation region, and having end portions facing each other; and a gate separation region disposed on the isolation region, and disposed between the end portions of the gate line structures facing each other and between the interlayer insulating layers. The gate separation region comprises a gap fill layer and a buffer structure, the buffer structure includes a buffer liner disposed between the gap fill layer and the isolation region, between the end portions of the gate line structures facing each other and side surfaces of the gap fill layer, and between the interlayer insulating layers and the side surfaces of the gap fill layer.

Some embodiments include an integrated assembly having a semiconductor-containing structure with a body region vertically between an upper region and a lower region. The upper region includes a first source/drain region. The lower region is split into two legs which are both joined to the body region. One of the legs includes a second source/drain region and the other of the legs includes a body contact region. The first and second source/drain regions are of a first conductivity type, and the body contact region is of a second conductivity type which is opposite to the first conductivity type. An insulative material is adjacent to the body region. A conductive gate is adjacent to the insulative material. A transistor includes the semiconductor-containing structure, the conductive gate and the insulative material. Some embodiments include methods of forming integrated assemblies.

A semiconductor device includes a gate structure on a substrate, a single diffusion break (SDB) structure adjacent to the gate structure, a first spacer adjacent to the gate structure, a second spacer adjacent to the SDB structure, a source/drain region between the first spacer and the second spacer, an interlayer dielectric (ILD) layer around the gate structure and the SDB structure, and a contact plug in the ILD layer and on the source/drain region. Preferably, a top surface of the second spacer is lower than a top surface of the first spacer.

The present disclosure relates to semiconductor structures and, more particularly, to a semiconductor device with a dual isolation structure and methods of manufacture. The structure includes: a dual isolation structure including semiconductor material; and an active device region including a channel material and a gate metal material over the channel material. The channel material is between the dual isolation structure and the gate metal material includes a bottom surface not extending beyond a sidewall of the dual isolation structure.

A method for manufacturing a microelectronic device from a semiconductor-on-insulator substrate, the device having active components formed in active areas of the substrate separated by isolation trenches and which are delimited by first sidewalls, the isolation trenches being filled, at least partially, with a first dielectric material, includes a step of chemically attacking a passive section of the first bottom of the isolation trenches configured to generate, at said section, a roughness quadratic mean comprised between 2 nm and 6 nm. The method also includes a step of forming a passive component covering the first dielectric material and directly above the passive section.

A method for making a semiconductor device includes forming a first fin structure, a second fin structure, and a third fin structure over a substrate. The first through third fin structures all extend along a first lateral direction, and the second fin structure is disposed between the first and third fin structures. The method includes forming a mold by filling up trenches between neighboring ones of the first through third fin structures with a first dielectric material. The method includes cutting the second fin structure by removing an upper portion of the second fin structure. The method includes replacing the upper portion of the second fin structure with a second dielectric material to form a dielectric cut structure. The method includes recessing the mold to expose upper portions of the first fin structure and the third fin structure, respectively.

A method for shallow trench isolation structures in a semiconductor device and a semiconductor device including the shallow trench isolation structures are disclosed. In an embodiment, the method may include forming a trench in a substrate; depositing a first dielectric liner in the trench; depositing a first shallow trench isolation (STI) material over the first dielectric liner, the first STI material being deposited as a conformal layer; etching the first STI material; depositing a second STI material over the first STI material, the second STI material being deposited as a flowable material; and planarizing the second STI material such that top surfaces of the second STI material are co-planar with top surfaces of the substrate.

A method of manufacturing a semiconductor device includes a trench forming step, a laser irradiation step and a peeling step. In the trench forming step, a trench is formed on a first main surface of a semiconductor substrate having a device structure formed thereon. In the laser irradiation step, a laser is irradiated from a second main surface of the semiconductor substrate to a plane surface that is positioned and extends at a predetermined depth of the semiconductor substrate. In the peeling step, a device layer is peeled off from the semiconductor substrate along the plane surface on which the laser is irradiated. The peeling step may be performed in a state in which the trenches are either unfilled or filled with a material having a lower coefficient of thermal expansion than the semiconductor substrate.

Provided in a semiconductor device including a substrate, an active region upwardly protruding from the substrate, a plurality of active fins upwardly protruding from the active region and extending in a first direction parallel to an upper surface of the substrate, the plurality of active fins being provided in a second direction that is parallel to the upper surface of the substrate and intersects with the first direction, and an isolation structure provided on the substrate, the isolation structure covering a sidewall of the active region and a lower portion of a sidewall of each of the plurality of active fins, wherein a first sidewall of the active region adjacent to a first active fin among the plurality of active fins has a staircase shape, the first active fin being provided on a first edge of the active region in the second direction.

A method for preparing a semiconductor device structure is provided. The method includes forming an isolation structure in a semiconductor substrate, and recessing the semiconductor substrate to form a first opening and a second opening. The first opening and the second opening are on opposite sides of the isolation structure, and a width of the second opening is greater than a width of the first opening. The method also includes forming an electrode layer over the semiconductor substrate. The first opening and the second opening are filled by the electrode layer. The method further includes polishing the electrode layer to form a gate electrode in the first opening and a resistor electrode in the second opening, and forming a source/drain (S/D) region in the semiconductor substrate. The S/D region is between the gate electrode and the isolation structure