A method for fabricating a trench isolation structure is provided. The method includes providing a substrate and forming a patterned mask layer on the substrate. A first etching step is performed on the substrate by using the patterned mask layer to form a trench in the substrate. A dielectric material is formed in the trench and on the patterned mask layer, wherein the dielectric material on the patterned mask layer has a first height. An etch back step is performed to decrease the dielectric material on the patterned mask layer to a second height. A planarization process is performed to remove the dielectric material on the patterned mask layer, where a polishing pad is used, and a first pressure and a second pressure are respectively applied on a central portion and a peripheral portion of the polishing pad, wherein the second pressure is greater than the first pressure.

A semiconductor device includes a substrate having a peripheral region and a cell region therein. A first semiconductor active pattern is provided, which protrudes from the substrate in the peripheral region. A second semiconductor active pattern is provided, which protrudes from the substrate in the cell region. A first edge of an upper portion of the first semiconductor active pattern has a rounded shape, and a second edge of an upper portion of the second semiconductor active pattern has a rounded shape. A curvature of the first edge is greater than a curvature of the second edge.

A method includes forming a metal-oxide-semiconductor field-effect transistor (MOSFET). The Method includes performing an implantation to form a pre-amorphization implantation (PAI) region adjacent to a gate electrode of the MOSFET, forming a strained capping layer over the PAI region, and performing an annealing on the strained capping layer and the PAI region to form a dislocation plane. The dislocation plane is formed as a result of the annealing, with a tilt angle of the dislocation plane being smaller than about 65 degrees.

Methods comprising forming a film on at least one feature of a substrate surface are described. The film is expanded to fill the at least one feature and cause growth of the film from the at least one feature. Methods of forming self-aligned vias are also described.

A method of manufacturing a semiconductor structure is provided. The method includes providing a semiconductor substrate having an active region, forming a fin structure in the active region, and forming a conductive element on the body portion and the first tapered portion of the fin structure. The fin structure includes a body portion, and a first tapered portion protruding from an upper surface of the body portion.

Integrated circuits with improved laterally diffused metal oxide semiconductor (LDMOS) structures, and methods of fabricating the same, are provided. An exemplary LDMOS integrated circuit includes an n-type reduced surface field, a p-type body well disposed on a lateral side of the n-type reduced surface field region, a shallow trench isolation structure disposed within the n-type reduced surface field region, and a gate structure disposed partially over the p-type body well, partially over the n-type reduced surface field region, partially over the shallow trench isolation structure, and partially within the shallow trench isolation structure.

A semiconductor structure includes a first semiconductor fin and a second semiconductor fin adjacent to the first semiconductor fin, a first epitaxial source/drain (S/D) feature disposed over the first semiconductor fin, a second epitaxial S/D feature disposed over the second semiconductor fin, an interlayer dielectric (ILD) layer disposed over the first and the second epitaxial S/D features, and an S/D contact disposed over and contacting the first epitaxial S/D feature, where a portion of the S/D contact laterally extends over the second epitaxial S/D feature, and the portion is separated from the second epitaxial S/D feature by the ILD layer.

A device includes a first transistor, a second transistor, and a dielectric structure. The first transistor is over a substrate and has a first gate structure. The second transistor is over the substrate and has a second gate structure. The dielectric structure is between the first gate structure and the second gate structure. The dielectric structure has a width increasing from a bottom position of the dielectric structure to a first position higher than the bottom position of the dielectric structure. A width of the first gate structure is less than the width of the dielectric structure at the first position.

A semiconductor structure includes a substrate having a first region and a second region around the first region. A first fin structure is disposed within the first region. A second fin structure is disposed within the second region. A first isolation trench is disposed within the first region and situated adjacent to the first fin structure. A first trench isolation layer is disposed in the first isolation trench. A second isolation trench is disposed around the first region and situated between the first fin structure and the second fin structure. The bottom surface of the second isolation trench has a step height. A second isolation layer is disposed in the second isolation trench.

A semiconductor structure includes a semiconductor substrate, a first isolation dam, a plurality of switching transistors and a second isolation dam. The semiconductor substrate includes a trench, an isolation region formed by a region where the trench is located, a plurality of active regions defined by the isolation region, and an electrical isolation layer, the electrical isolation layer being located on one side, away from an opening of the trench, of the trench; the first isolation dam fills the trench; the switching transistor is at least partially embedded in the active region of the semiconductor substrate; and the second isolation dam is at least partially located between the first isolation dam and the electrical isolation layer.