A semiconductor device includes a semiconductor substrate, a semiconductor fin protruding from the semiconductor substrate, and an isolation layer disposed above the semiconductor substrate. The isolation layer includes a first portion disposed on a first sidewall of the semiconductor fin and a second portion disposed on a second sidewall of the semiconductor fin. Top surfaces of the first and second portions of the isolation layer are leveled. The first portion of the isolation layer includes an air pocket. The semiconductor device also includes a dielectric fin with a bottom portion embedded in the second portion of the isolation layer.

A device includes a semiconductor substrate and implant isolation region extending from a top surface of the semiconductor substrate into the semiconductor substrate surrounding an active region. A gate dielectric is disposed over an active region of the semiconductor substrate, wherein the gate dielectric extends over the implant isolation region. A gate electrode is disposed over the gate dielectric and an end cap dielectric layer is between the gate dielectric and the gate electrode over the implant isolation region.

In described examples, a device includes a semiconductor substrate; a buried layer; and a trench with inner walls extending from the buried layer to a surface of the semiconductor substrate, the trench having sidewalls, a bottom wall, a barrier layer including a titanium (Ti) layer covering the sidewalls and the bottom wall, and a filler including more than one layer of conductor material formed on the barrier layer.

A method for manufacturing a trench isolation structure comprising forming a shallow trench having a wider upper section and a narrower lower section in a wafer surface, removing part of the silicon oxide by etching, forming a silicon oxide corner structure at a corner at a top corner of the shallow trench by thermal oxidation, depositing silicon nitride on the wafer surface to cover surfaces of the shallow trench silicon oxide and the silicon oxide corner structure, dry etching the silicon nitride on the shallow trench silicon oxide surface thereby forming masking silicon nitride residues extending into the trench, etching downwards to form a deep trench, forming silicon oxide layers on a side wall and the bottom of the deep trench, depositing polycrystalline silicon in the shallow and deep trenches, removing the silicon nitride, and forming silicon oxide in the shallow trench to cover the polycrystalline silicon.

A solid-state imaging element of an embodiment of the present disclosure includes: a semiconductor substrate including a photoelectric conversion section for each pixel; a pixel transistor provided on one surface of the semiconductor substrate; and an element separation section provided in the semiconductor substrate and including a first element separation section and a second element separation section that have mutually different configurations, the element separation section defining an active region of the pixel transistor, in which the second element separation section has, on a side surface, a first semiconductor region and a second semiconductor region that have mutually different impurity concentrations in a depth direction of the second element separation section.

The embodiments of mechanisms for doping wells of finFET devices described in this disclosure utilize depositing doped films to dope well regions. The mechanisms enable maintaining low dopant concentration in the channel regions next to the doped well regions. As a result, transistor performance can be greatly improved. The mechanisms involve depositing doped films prior to forming isolation structures for transistors. The dopants in the doped films are used to dope the well regions near fins. The isolation structures are filled with a flowable dielectric material, which is converted to silicon oxide with the usage of microwave anneal. The microwave anneal enables conversion of the flowable dielectric material to silicon oxide without causing dopant diffusion. Additional well implants may be performed to form deep wells. Microwave anneal(s) may be used to anneal defects in the substrate and fins.

Before formation of gate insulating films, an oblique ion implantation of oxygen into opposing sidewalls of trenches, from a top of an oxide film mask is performed, forming oxygen ion-implanted layers in surface regions of the sidewalls. A peak position of oxygen concentration distribution of the oxygen ion-implanted layers is inside the oxide film mask. After removal of the oxide film mask, HTO films constituting the gate insulating films are formed. During deposition of the HTO films, excess carbon occurring at the start of the deposition of the HTO films and in the gate insulating films reacts with oxygen in the oxygen ion-implanted layers, thereby becoming an oxocarbon and being desorbed. The oxygen ion-implanted layers have a thickness in a direction orthogonal to the sidewalls at most half of the thickness of the gate insulating films, and an oxygen concentration higher than any other portion of the semiconductor substrate.

A semiconductor structure and a forming method thereof are provided. One form of the forming method includes: providing a base, where a well region and a drift region adjacent to the well region are formed in the base; forming a trench in the drift region; forming a diffusion barrier layer in the trench; after the diffusion barrier layer is formed, forming a gate structure on the base at a junction between the well region and the drift region, where the gate structure is located on a side of the diffusion barrier layer near the well region; and forming a source region in the well region on one side of the gate structure, and forming a drain region in the drift region on the other side of the gate structure, where the drain region is located on a side of the diffusion barrier layer in the drift region away from the well region. In embodiments and implementations of the present disclosure, during the operation of the semiconductor structure, under the barrier action of the diffusion barrier layer, doping ions in the drain region do not easily diffuse into the channel region below the gate structure, which makes a depletion layer of the source region and the drain region on two sides of the gate structure not easily expand, thereby being beneficial to alleviate the short-channel effect, and further improving the electrical performance of the semiconductor structure.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first conductive body, a second conductive body positioned separate from the first conductive body, a plurality of liners respectively correspondingly attached to a side surface of the first conductive body and a side surface of the second conductive body, and a first insulating segment positioned between the first conductive body and the second conductive body.

A semiconductor device includes a first isolation structure extending through an upper portion of a substrate and defining a first active region, a first gate structure on the substrate, and first source/drain regions at upper portions of the first active region adjacent to the first gate structure. The first isolation structure includes an upper isolation pattern structure and a lower isolation pattern. The upper isolation pattern structure includes a first isolation pattern and a second isolation pattern covering a sidewall of the first isolation pattern. The lower isolation pattern is formed under and contacting the upper isolation pattern structure, and a width of the lower isolation pattern is greater than a width of the upper isolation pattern structure.