A method includes forming a semiconductor layer on a semiconductor substrate. The semiconductor layer is patterned to form a semiconductive structure. Each of widths of two ends of the semiconductive structure is wider than a width of a middle of the semiconductive structure. The semiconductive structure is doped to form a doped semiconductor structure. An isolation structure is formed to surround the doped semiconductor structure. A recessing process is performed such that two trenches are formed on the doped semiconductor structure, and first, second and third portions of an active region are formed on the semiconductor substrate. A first gate structure and a second gate structure are formed in the trenches such that the first portion and the third portion are partially spaced apart by the first gate structure, and the second portion and the third portion are partially spaced apart by the second gate structure.

Semiconductor structures including electrical isolation and methods of forming a semiconductor structure including electrical isolation. Shallow trench isolation regions extend from a top surface of a semiconductor substrate into the semiconductor substrate. The semiconductor substrate contains single-crystal semiconductor material, and the shallow trench isolation regions are positioned to surround an active device region of the semiconductor substrate. A polycrystalline layer is formed in the semiconductor substrate. The polycrystalline layer has a first section beneath the active device region and a second section beneath the plurality of shallow trench isolation regions. The first section of the polycrystalline layer is located at a different depth relative to the top surface of the semiconductor substrate than the second section of the polycrystalline layer.

A semiconductor structure includes an active region, an isolation structure, a first gate structure, and a second gate structure. The active region is disposed over a semiconductor substrate and has a first portion, a second portion, and a third portion. The third portion is between the first portion and the second portion. A shape of the first portion is different from a shape of the third portion, in a top view. The isolation structure is disposed over the semiconductor substrate and surrounds the active region. The first gate structure is disposed between the first portion and the third portion of the active region. The second gate structure is disposed between the second portion and the third portion of the active region.

A method of fabricating an image sensor is provided. The method includes comprises forming a deep trench in a semiconductor substrate, performing a first plasma doping process to form a first impurity region a portion of in the semiconductor substrate adjacent to inner sidewalls and a bottom surface of the deep trench, the first impurity region being doped with first impurities of a first conductivity type, and performing an annealing process to diffuse the first impurities from the first impurity region into the semiconductor substrate to form a photoelectric conversion part.

A method of providing electrical isolation between subsections in a waveguide structure for a photonic integrated device, the structure comprising a substrate, a buffer layer and a core layer, the buffer layer being located between the substrate and the core and comprising a dopant of a first type, the first type being either n-type or p- type, the method comprising the steps of prior to adding any layer to a side of the core layer opposite to the buffer layer: selecting at least one area to be an electrical isolation region, applying a dielectric mask to a surface of the core layer opposite to the buffer layer, with a window in the mask exposing an area of the surface corresponding to the selected electrical isolation region, implementing diffusion of a dopant of a second type, the second type being of opposite polarity to the first type, and allowing the dopant of the second type to penetrate to the substrate to form a blocking junction.

A semiconductor device structure may include a substrate having a substrate base comprising a first dopant type; a semiconductor layer disposed on a surface of the substrate base, the semiconductor layer comprising a second dopant type and having an upper surface; and a semiconductor plug assembly comprising a semiconductor plug disposed within the semiconductor layer, the semiconductor plug extending from an upper surface of the semiconductor layer and having a depth at least equal to a thickness of the semiconductor layer, the semiconductor plug having a first boundary, the first boundary formed within the semiconductor layer, and having a second boundary, the second boundary formed within the semiconductor layer and disposed opposite the first boundary, wherein the first boundary and second boundary extend perpendicularly to the surface of the substrate base.

A semiconductor device structure may include a substrate having a substrate base comprising a first dopant type; a semiconductor layer disposed on a surface of the substrate base, the semiconductor layer comprising a second dopant type and having an upper surface; and a semiconductor plug assembly comprising a semiconductor plug disposed within the semiconductor layer, the semiconductor plug extending from an upper surface of the semiconductor layer and having a depth at least equal to a thickness of the semiconductor layer, the semiconductor plug having a first boundary, the first boundary formed within the semiconductor layer, and having a second boundary, the second boundary formed within the semiconductor layer and disposed opposite the first boundary, wherein the first boundary and second boundary extend perpendicularly to the surface of the substrate base.

A semiconductor structure includes a substrate having a first region and a second region defined thereon, a first isolation in the first region, a second isolation in the second region, and a region surrounding the first isolation in the substrate. The substrate includes a first material, and the region includes the first material and a second material. The first isolation has a first width, the second isolation has a second width, and the first width is greater than the second width. A bottom and sidewalls of the first isolation are in contact with the region, and a bottom and sidewalls of the second isolation are in contact with the substrate.

A semiconductor device includes etch stop films formed on the first gate electrode, the first source region, the first drain region, and the shallow trench isolation regions, respectively. First interlayer insulating films are formed on the etch stop film, respectively. Deep trenches are formed in the substrate between adjacent ones of the first interlayer insulating films to overlap the shallow trench isolation regions. Sidewall insulating films are formed in the deep trenches, respectively. A gap-fill insulating film is formed on the sidewall insulating film. A second interlayer insulating film is formed on the gap-fill insulating film. A top surface of the second interlayer insulating film is substantially planar and a bottom surface of the second interlayer insulating film is undulating.

Structures and processes for improving radiation hardness and eliminating latch-up in integrated circuits are provided. An example process includes forming a first doped buried layer, a first well, and a second well, and using a first mask, forming a second doped buried layer only in a first region above the first doped buried layer and between at least the first well and the second well, where the first mask is configured to control spacing between the wells and the doped buried layers. The process further includes using a second mask, forming a vertical conductor located only in a second region above the first region and between at least the first well and the second well, where the vertical conductor is doped to provide a low resistance link between the second doped buried layer and at least a top surface of the substrate.