A device includes a semiconductive substrate, a stop layer, a semiconductive fin, a fin isolation structure, and a source/drain epitaxial layer. The stop layer is over the semiconductive substrate and includes SiGeO.sub.x, SiGe, SiP or SiPO.sub.x, where x is greater than 0. The semiconductive fin is over the stop layer. The fin isolation structure is connected to a sidewall of the semiconductive fin. The source/drain epitaxial layer is adjacent to the semiconductive fin. The semiconductive fin is between the source/drain epitaxial layer and the fin isolation structure.

The present disclosure provides a method of manufacturing a semiconductor device. The method includes steps of providing a patterned mask having a plurality of openings on a substrate; etching the substrate through the openings to form an etched substrate and a trench in the etched substrate, wherein the etched substrate comprises a protrusion; introducing dopants having a first conductivity type in the etched substrate and on either side of the trench to form a plurality of first impurity regions; forming an isolation film in the trench; and depositing a conductive material on the isolation film.

A method includes: doping a region through a first surface of a semiconductor substrate; forming a plurality of doped structures within the semiconductor substrate, wherein each of the plurality of doped structures extends along a vertical direction and is in contact with the doped region; forming a plurality of transistors over the first surface, wherein each of the transistors comprises one or more source/drain structures electrically coupled to the doped region through a corresponding one of the doped structures; forming a plurality of interconnect structures over the first surface, wherein each of the interconnect structures is electrically coupled to at least one of the transistors; and testing electrical connections between the interconnect structures and the transistors based on detecting signals present on the doped region through a second surface of the semiconductor substrate, the second surface opposite to the first surface.

Methods for simultaneous generation of a buried oxide (BOX) layer and a trap-rich layer in a silicon substrate are presented. According to one aspect, oxygen is implanted in the silicon substrate such as to form a region of oxygen concentration according to a concentration profile with a peak at a target depth of the BOX layer. According to another aspect, the concentration profile includes a leading-edge profile that is shorter than a trailing-edge profile. According to another aspect, the substrate is annealed to form the BOX layer and a damaged layer immediately below the BOX layer, the damaged layer having a functionality of a trap-rich layer.

A lateral double-diffused metal oxide semiconductor component and a manufacturing method therefor. The lateral double-diffused metal oxide semiconductor component comprises: a semiconductor substrate, the semiconductor substrate being provided thereon with a drift area; the drift area being provided therein with a trap area and a drain area, the trap area being provided therein with an active area and a channel; the drift area being provided therein with a deep trench isolation structure arranged between the trap area and the drain area, and the deep trench isolation structure being provided at the bottom thereof with alternately arranged first p-type injection areas and first n-type injection areas.

A method for fabricating a semiconductor device includes forming a low-k dielectric layer, forming a pattern by etching the low-k dielectric layer, and implanting a carbon-containing material into a surface of the pattern.

A method is disclosed for promoting the formation of uniform platelets in a monocrystalline semiconductor donor substrate by irradiating the monocrystalline semiconductor donor substrate with light. The photon-absorption assisted platelet formation process leads to uniformly distributed platelets with minimum built-in stress that promote the formation a well-defined cleave-plane in the subsequent layer transfer process.

A method includes forming a first semiconductor fin and a second semiconductor fin parallel to each other and protruding higher than top surfaces of isolation regions. The isolation regions include a portion between the first and the second semiconductor fins. The method further includes forming a gate stack crossing over the first and the second semiconductor fins, etching a portion of the gate stack to form an opening, wherein the portion of the isolation regions, the first semiconductor fin, and the second semiconductor fin are exposed to the opening, etching the first semiconductor fin, the second semiconductor fin, and the portion of the isolation regions to extend the opening into a bulk portion of a semiconductor substrate below the isolation regions, and filling the opening with a dielectric material to form a cut-fin isolation region.

A method and related structure provide a void-free dielectric over trench isolation region in an FDSOI substrate. The structure may include a first transistor including a first active gate over the substrate, a second transistor including a second active gate over the substrate, a first liner extending over the first transistor, and a second, different liner extending over the second transistor. A trench isolation region electrically isolates the first transistor from the second transistor. The trench isolation region includes a trench isolation extending into the FDSOI substrate and an inactive gate over the trench isolation. A dielectric extends over the inactive gate and in direct contact with an upper surface of the trench isolation region. The dielectric is void-free, and the liners do not extend over the trench isolation.

A semiconductor-on-insulator (SOI) device including a handle wafer, a buried oxide (BOX), and a top device layer is provided. A plurality of elongated trenches are formed in the handle wafer. Air gaps are formed in the elongated trenches by pinching off each of the elongated trenches. In one approach, prior to the pinching off, a plurality of lateral openings are formed contiguous with the elongated trenches and adjacent to the BOX. The elongated trenches and/or the lateral openings reduce parasitic capacitance between the handle wafer and the top device layer. In another approach, sidewalls of the elongated trenches are implant-damaged so as to further reduce the parasitic capacitance between the handle wafer and the top device layer.