H01L21/76248

NANOSHEET TRANSISTOR BOTTOM ISOLATION
20210151558 · 2021-05-20 ·

Semiconductor devices and methods of forming the same include forming slanted dielectric structures from a first dielectric material on a substrate, with gaps between adjacent slanted dielectric structures. A first semiconductor layer is grown from the substrate, using a first semiconductor material, including a lower portion that fills the gaps and an upper portion above the first dielectric material. The lower portion of the first semiconductor layer is replaced with additional dielectric material.

Devices with backside metal structures and methods of formation thereof

A semiconductor device includes a first epitaxial layer, a second epitaxial layer disposed below the first epitaxial layer, a conductive layer disposed below and directly contacting the second epitaxial layer, and a plurality of spacers disposed between the second epitaxial layer and the conductive layer. The conductive layer includes a metal. The plurality of spacers include a bulk semiconductor material.

Method for producing a semiconductor chip and semiconductor chip

A method for producing a semiconductor chip (100) is provided, in which, during a growth process for growing a first semiconductor layer (1), an inhomogeneous lateral temperature distribution is created along at least one direction of extent of the growing first semiconductor layer (1), such that a lateral variation of a material composition of the first semiconductor layer (1) is produced. A semiconductor chip (100) is additionally provided.

Nanosheet transistor bottom isolation

Semiconductor devices and methods of forming the same include forming slanted dielectric structures from a first dielectric material on a substrate, with gaps between adjacent slanted dielectric structures. A first semiconductor layer is grown from the substrate, using a first semiconductor material, including a lower portion that fills the gaps and an upper portion above the first dielectric material. The lower portion of the first semiconductor layer is replaced with additional dielectric material.

FABRICATION METHOD OF INTEGRATED CIRCUIT SEMICONDUCTOR DEVICE

A fabrication method of an integrated circuit semiconductor device includes: forming a plurality of low dielectric pattern apart from each other on a substrate, the plurality of low dielectric pattern having a lower dielectric constant than the substrate; after forming the low dielectric pattern, forming a flow layer to bury the low dielectric pattern on the substrate; forming an epitaxial layer on the flow layer; and forming a transistor in the substrate comprising the low dielectric pattern buried by the flow layer and in the epitaxial layer.

SOI substrate manufacturing method and SOI substrate
10804137 · 2020-10-13 · ·

An SOI substrate manufacturing method and an SOI substrate are provided, where the method includes: forming a patterned etch-stop layer in an oxide layer of a first silicon substrate, bonding a surface, having the patterned etch-stop layer (130), of the first silicon substrate with a surface of a second silicon substrate, and peeling off a part of the first silicon substrate to form a patterned SOI substrate.

EPITAXIALLY FABRICATED HETEROJUNCTION BIPOLAR TRANSISTORS

Techniques are disclosed for forming a heterojunction bipolar transistor (HBT) that includes a laterally grown epitaxial (LEO) base layer that is disposed between corresponding emitter and collector layers. Laterally growing the base layer of the HBT improves electrical and physical contact between electrical contacts to associated portions of the HBT device (e.g., a collector). By improving the quality of electrical and physical contact between a layer of an HBT device and corresponding electrical contacts, integrated circuits using HBTs are better able to operate at gigahertz frequency switching rates used for modern wireless communications.

NANOSHEET TRANSISTOR BOTTOM ISOLATION
20200295130 · 2020-09-17 ·

Semiconductor devices and methods of forming the same include forming slanted dielectric structures from a first dielectric material on a substrate, with gaps between adjacent slanted dielectric structures. A first semiconductor layer is grown from the substrate, using a first semiconductor material, including a lower portion that fills the gaps and an upper portion above the first dielectric material. The lower portion of the first semiconductor layer is replaced with additional dielectric material.

OXIDIZED CAVITY STRUCTURES WITHIN AND UNDER SEMICONDUCTOR DEVICES

The present disclosure relates to semiconductor structures and, more particularly, to oxidized cavity structures within and under semiconductor devices and methods of manufacture. The structure includes: a substrate material; active devices over the substrate material; an oxidized trench structure extending into the substrate and surrounding the active devices; and one or more oxidized cavity structures extending from the oxidized trench structure and formed in the substrate material under the active devices.

Devices with Backside Metal Structures and Methods of Formation Thereof

A semiconductor device includes a first epitaxial layer, a second epitaxial layer disposed below the first epitaxial layer, a conductive layer disposed below and directly contacting the second epitaxial layer, and a plurality of spacers disposed between the second epitaxial layer and the conductive layer. The conductive layer includes a metal. The plurality of spacers include a bulk semiconductor material.