Integrated circuit (IC) interconnect lines having improved electromigration resistance. Multi-patterning may be employed to define a first mask pattern. The first mask pattern may be backfilled and further patterned based on a second mask layer through a process-based selective occlusion of openings defined in the second mask layer that are below a threshold minimum lateral width. Portions of material underlying openings defined in the second mask layer that exceed the threshold are removed. First trenches in an underlying dielectric material layer may be etched based on a union of the remainder of the first mask layer and the partially occluded second mask layer. The first trenches may then be backfilled with a first conductive material to form first line segments. Additional trenches in the underlayer may then be etched and backfilled with a second conductive material to form second line segments that are coupled together by the first line segments.

In one exemplary aspect, a method comprises providing a semiconductor structure having a substrate, one or more first dielectric layers over the substrate, a first metal plug in the one or more first dielectric layers, and one or more second dielectric layers over the one or more first dielectric layers and the first metal plug. The method further comprises etching a via hole into the one or more second dielectric layers to expose the first metal plug, etching a top surface of the first metal plug to create a recess thereon, and applying a metal corrosion protectant comprising a metal corrosion inhibitor to the top surface of the first metal plug.

A method of forming a semiconductor device includes: depositing a first conductive plate and a second conductive plate adjacent to the first conductive plate; depositing a first insulating plate on the first conductive plate and the second conductive plate; depositing a third conductive plate on the first insulating plate; depositing a second insulating plate on the third conductive plate; forming a fourth conductive plate on the second insulating plate; forming a first conductive via penetrating the fourth conductive plate, the second insulating plate, the first insulating plate, and the first conductive plate; and forming a second conductive via penetrating the second insulating plate, the third conductive plate, the first insulating plate, and the second conductive plate.

A semiconductor device includes a substrate, a lower structure on the substrate, the lower structure including a first wiring structure, a second wiring structure, and a lower insulating structure covering the first and second wiring structures, a first pattern layer including a plate portion and a via portion, the plate portion being on the lower insulating structure and the via portion extending into the lower insulating structure from a lower portion of the plate portion and overlapping the first wiring structure, a graphene-like carbon material layer in contact with the via portion and the first wiring structure between the via portion and the first wiring structure, gate layers stacked in a vertical direction perpendicular to an upper surface of the substrate and spaced apart from each other on the first pattern layer, and a memory vertical structure penetrating through the gate layers in the vertical direction.

A semiconductor interconnect structure and its manufacturing method are presented. The manufacturing method includes: providing a substrate structure, wherein the substrate structure comprises: a substrate; a first metal layer on the substrate; a dielectric layer on the substrate, wherein the dielectric layer covers the first metal layer, and wherein the dielectric layer has a hole extending to the first metal layer; and a hard mask layer on the dielectric layer; removing the hard mask layer on the dielectric layer; selectively depositing a second metal layer at the bottom of the hole; and depositing a third metal layer, wherein the third metal layer fills the hole.

This semiconductor interconnect structure provides improved reliability over conventional structures.

A method for manufacturing a semiconductor device includes providing a substrate structure having an action region and a gate structure having a gate dielectric layer, a gate, a hardmask. The method also includes forming a first dielectric layer on the gate structure, forming a second dielectric layer on the first dielectric layer, performing a surface treatment on the second dielectric layer so that the upper surface of the second dielectric layer is flush with the upper surface of the mask member, which has a first recess is in its middle portion, forming a third dielectric layer on the second dielectric layer covering the mask member and selectively etching the third dielectric layer and the second dielectric layer relative to the first dielectric layer and the hardmask to form an opening adjacent to the gate structure and exposing the first dielectric layer on sidewalls of the gate structure.

A semiconductor device according to an embodiment includes: a stacked body including a plurality of first conductive films stacked via an inter-layer insulating film;

a first conductive body contacting the stacked body to extend in a stacking direction; and a plurality of first insulating films in the same layers as the first conductive films and disposed between the first conductive body and the first conductive films, the first conductive body including a projecting part that projects along tops of one of the first insulating films and one of the first conductive films, and a side surface of the projecting part contacting an upper surface of the one of the first conductive films.

In one embodiment, a semiconductor device includes a first contact pad disposed at a top side of a workpiece, a second contact pad disposed at the top side of the workpiece. An isolation region is disposed between the first contact pad and the second contact pad. A metal strip is disposed at least partially within the isolation region. The metal strip is not coupled to an external potential node.

An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. A multi-layer dielectric film is formed along sidewalls of the first opening. One or more etch processes form one or more spacer-shaped structures along sidewalls of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits. A dielectric liner is formed, and the opening is filled with a conductive material to form a conductive plug.

A method includes bonding a die to a substrate, where the substrate has a first redistribution structure, the die has a second redistribution structure, and the first redistribution structure is bonded to the second redistribution structure. A first isolation material is formed over the substrate and around the die. A first conductive via is formed, extending from a first surface of the substrate, where the first surface is opposite the second redistribution structure, the first conductive via contacting a first conductive element in the second redistribution structure. Forming the first conductive via includes patterning an opening in the substrate, extending the opening to expose the first conductive element, where extending the opening includes using a portion of a second conductive element in the first redistribution structure as an etch mask, and filling the opening with a conductive material.