Patent classifications
H01L21/76817
METHOD FOR VIA FORMATION BY MICRO-IMPRINTING
A method and apparatus for forming a plurality of vias in panels for advanced packaging applications is disclosed, according to one embodiment. A redistribution layer is deposited on a substrate layer. The redistribution layer may be deposited using a spin coating process, a spray coating process, a drop coating process, or lamination. The redistribution layer is then micro-imprinted using a stamp inside a chamber. The redistribution layer and the stamp are then baked inside the chamber. The stamp is removed from the redistribution layer to form a plurality of vias in the redistribution layer. Excess residue built-up on the redistribution layer may be removed using a descumming process. A residual thickness layer disposed between the bottom of each of the plurality of vias and the top of the substrate layer may have thickness of less than about 1 μm.
METHOD FOR MANUFACTURING ELECTRONIC COMPONENT DEVICE
Disclosed is a method for manufacturing an electronic component including: forming a via hole extending in a thickness direction of a curable sealing resin layer provided on a base material by an imprint method of pressing a mold into the sealing resin layer from a side opposite to the base material; curing the sealing resin layer; filling the via hole with a conductor precursor; and forming a conductive via by heating the conductor precursor filled in the via hole.
Manufacturing method of original plate and semiconductor device
According to one embodiment, an original plate for imprint lithography has a first surface side having a patterned portion thereon. The patterned portion includes a groove having a bottom surface recessed from a first surface to a first depth, and a columnar portion on the bottom surface and protruding from the bottom surface to extend beyond the first surface. The original plate may be used to form replica templates by imprint lithography processes. The replica templates can be used in semiconductor device manufacturing processes or the like.
Wiring structure and method of manufacturing the same, semiconductor device, multilayer wiring structure and method of manufacturing the same, semiconductor element mounting substrate, method of forming pattern structure, imprint mold and method of manufacturing the same, imprint mold set, and method of manufacturing multilayer wiring board
A mold includes a mold base material and a rugged structure located at a main surface of the mold base material. The rugged structure includes a plurality of linearly shaped projected portions for forming wiring, and a circularly shaped projected portion for forming a pad portion, in which a light-shielding layer is provided at a top portion flat surface of the circularly shaped projected portion for forming the pad portion.
Direct application additive manufacturing for conductive wafer interconnect
An improved silicon carbide wafer using direct application conductive ink interconnects positioned on printing connection pads. The conductive ink interconnected can be routed to form a custom length resistive trace for a device after fabrication and measurement of the device.
MANUFACTURING METHOD OF ORIGINAL PLATE AND SEMICONDUCTOR DEVICE
According to one embodiment, an original plate for imprint lithography has a first surface side having a patterned portion thereon. The patterned portion includes a groove having a bottom surface recessed from a first surface to a first depth, and a columnar portion on the bottom surface and protruding from the bottom surface to extend beyond the first surface. The original plate may be used to form replica templates by imprint lithography processes. The replica templates can be used in semiconductor device manufacturing processes or the like.
Template, template manufacturing method, and semiconductor device manufacturing method
According to one embodiment, a template is provided with a transferring pattern on a first surface of a substrate. The transferring pattern includes a first projecting portion that projects from the first surface with a first height and extends in a first direction along the first surface, a second projecting portion that projects from the first surface with a second height higher than the first height and extends in a second direction along the first surface, a first columnar portion that is arranged at a position overlapping with the first projecting portion and has a top surface with a third height higher than the second height as a height from the first surface, and a second columnar portion that is arranged at a position overlapping with the second projecting portion and has a top surface with the third height as a height from the first surface.
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
In a frame member including a first region and a second region that are extending in a first direction in parallel to each other while being spaced apart from each other, first and second plating films are formed in the first and second regions, respectively. The second plating film is different in a type from the first plating film. Then, a stamping process is performed to the frame member including the first region and the second region, thereby a lead frame including a plurality of leads is formed. The lead frame includes a first lead group and a second lead group. The first plating film is formed in the first lead group, but the second plating film is not formed in the first lead group. Meanwhile, the second plating film is formed in the second lead group, but the first plating film is not formed in the second lead group.
Process of realization of an area of individualization of an integrated circuit
A method for producing an individualisation area includes providing at least a first level of the electrical tracks. The method includes depositing a dielectric layer and a deformable layer on the interconnection level. The method includes producing, in an area of the deformable layer, recessed patterns, by penetrating an imprint mould into the deformable layer, the production of the patterns being configured so that the patterns have a randomness in the deformable layer, thus forming random patterns. The method includes transferring the random patterns into the dielectric layer to form transferred random patterns therein and exposing the vias located in line with the transferred random patterns. The method includes filling the transferred random patterns with an electrically conductive material so as to form electrical connections between vias. The method includes producing a second level of the electrical tracks on the vias and the electrical connections.
Fluoropolymer stamp fabrication method
An imprint lithography stamp includes a stamp body having a patterned surface and formed from a fluorinated ethylene propylene copolymer. The imprint lithography stamp further includes a backing plate with a plurality of through-holes with portions of the stamp body extending into the through-holes to adhere the stamp body to the backing plate. The patterned surface of the stamp body has a plurality of protrusions extending from the stamp body, which are used to form high aspect ratio features at high processing temperatures. A mold design for forming the imprint lithography stamp and an injection molding process for forming the imprint lithography stamp are also provided.