Patent classifications
H01L21/76817
PATTERN FORMING METHOD AND IMPRINT APPARATUS
A pattern forming method includes forming a first resist pattern on a substrate using imprint lithography. And forming a resist onto the substrate at least at positions corresponding to a second resist pattern and then curing the resist to form the a second resist pattern on the substrate.
Wiring structure and method of manufacturing the same, semiconductor device, multilayer wiring structure and method of manufacturing the same, semiconductor element mounting substrate, method of forming pattern structure, imprint mold and method of manufacturing the same, imprint mold set, and method of manufacturing multilayer wiring board
A mold includes a mold base material and a rugged structure located at a main surface of the mold base material. The rugged structure includes a plurality of linearly shaped projected portions for forming wiring, and a circularly shaped projected portion for forming a pad portion, in which a light-shielding layer is provided at a top portion flat surface of the circularly shaped projected portion for forming the pad portion.
Mold chase for integrated circuit package assembly and associated techniques and configurations
Embodiments of the present disclosure are directed towards a mold chase for integrated circuit package assembly and associated techniques and configurations. In one embodiment, a method includes receiving a package substrate, the package substrate including a first die mounted on the package substrate by a plurality of first interconnect structures, and a plurality of second interconnect structures disposed on the package substrate and to route electrical signals of a second die, protecting a top surface of individual interconnect structures of the plurality of second interconnect structures from deposition of a mold material, and depositing the mold material on the package substrate between the individual interconnect structures of the plurality of second interconnect structures. Other embodiments may be described and/or claimed.
Method for patterning mesoporous inorganic oxide film, and electric device including mesoporous inorganic oxide film patterned by the same
Provided are a method for patterning a mesoporous inorganic oxide film, the method including a step of forming a mesoporous inorganic oxide film using a composition containing inorganic oxide particles; and a step of forming a pattern on the mesoporous inorganic oxide film using an elastic stamp for pattern formation, and then calcining the mesoporous inorganic oxide, and an electronic device including a mesoporous inorganic oxide film that has been patterned by the patterning method.
Template, method of manufacturing template, and method of manufacturing semiconductor device
According to one embodiment, there is provided a template including: a substrate having a first surface; a trench that is recessed from the first surface at a predetermined depth and extends along the first surface in a first direction, the trench includes a first portion having a second width in a second direction intersecting with the first direction and a second portion having a third width in the second direction; and a hole that is arranged is the first portion of the trench and extends from a bottom surface of the trench, and the first width is smaller than the second width, and the third width is smaller than the first width.
ENHANCING LIGHT EXTRACTION OF ORGANIC LIGHT EMITTING DIODES VIA NANOSCALE TEXTURING OF ELECTRODE SURFACES
An organic light emitting device is described, having an OLED including an anode, a cathode, and at least one organic layer between the anode and cathode. At least a portion of an electrode surface includes a plurality of scattering structures positioned in a partially disordered pattern resembling nodes of a two dimensional lattice. The scattering structures are positioned around the nodes of the two dimensional lattice with the average distance between the position of each scattering structure and a respective node of the lattice is from 0 to 0.5 of the distance between adjacent lattice nodes. A method of manufacturing an organic light emitting device and a method of enhancing the light-extraction efficiency of an organic light emitting device are also described.
TRENCH SILICIDE WITH SELF-ALIGNED CONTACT VIAS
A modified trench metal-semiconductor alloy formation method involves depositing a layer of a printable dielectric or a sacrificial carbon material within a trench structure and over contact regions of a semiconductor device, and then selectively removing the printable dielectric or sacrificial carbon material to segment the trench and form plural contact vias. A metallization layer is formed within the contact vias and over the contact regions.
Trench silicide with self-aligned contact vias
A modified trench metal-semiconductor alloy formation method involves depositing a layer of a printable dielectric or a sacrificial carbon material within a trench structure and over contact regions of a semiconductor device, and then selectively removing the printable dielectric or sacrificial carbon material to segment the trench and form plural contact vias. A metallization layer is formed within the contact vias and over the contact regions.
METHOD OF MANUFACTURING POROUS BODY, POROUS BODY, METHOD OF MANUFACTURING DEVICE, DEVICE, METHOD OF MANUFACTURING WIRING STRUCTURE, AND WIRING STRUCTURE
Provided are a method of manufacturing a porous body capable of easily manufacturing a porous body, a porous body, a method of manufacturing a device, a device, a method of manufacturing a wiring structure, and a wiring structure.
A photocurable composition including a condensing gas and a polymerizable compound is applied to a substrate or a mold, the photocurable composition is sandwiched between the substrate and the mold and then the photocurable composition is irradiated with light to cure the photocurable composition, and the mold is released from a surface of the cured photocurable composition.
Methods and devices for back end of line via formation
Back end of line via formation for semiconductor devices and methods of fabricating the semiconductor devices. One method includes, for instance: obtaining a wafer with a substrate and at least one contact in the substrate; depositing at least one lithography stack over the substrate; performing lithography to pattern at least one via opening; depositing a block co-polymer coating over the wafer into the at least one via opening; performing an ashing to remove excess block co-polymer material and form block co-polymer caps; and performing a thermal bake to separate the block co-polymer caps into a first material and a second material. An intermediate semiconductor device is also disclosed.