A method and structure for doping source and drain (S/D) regions of a PMOS and/or NMOS FinFET device are provided. In some embodiments, a method includes providing a substrate including a fin extending therefrom. In some examples, the fin includes a channel region, source/drain regions disposed adjacent to and on either side of the channel region, a gate structure disposed over the channel region, and a main spacer disposed on sidewalls of the gate structure. In some embodiments, contact openings are formed to provide access to the source/drain regions, where the forming the contact openings may etch a portion of the main spacer. After forming the contact openings, a spacer deposition and etch process may be performed. In some cases, after performing the spacer deposition and etch process, a silicide layer is formed over, and in contact with, the source/drain regions.

A semiconductor structure includes a semiconductor substrate, a gate structure, an etch stop layer, a dielectric structure, and a conductive material. The gate structure is on the semiconductor substrate. The etch stop layer is over the gate structure. The dielectric structure is over the etch stop layer, in which the dielectric structure has a ratio of silicon to nitrogen varying from a middle layer of the dielectric structure to a bottom layer of the dielectric structure. The conductive material extends through the dielectric structure.

A method of forming an interconnection structure is disclosed, including providing a substrate, forming a patterned layer on the substrate, the patterned layer comprising at least a trench formed therein, depositing a first dielectric layer on the patterned layer and sealing an air gap in the trench, depositing a second dielectric layer on the first dielectric layer and completely covering the patterned layer, and performing a curing process to the first dielectric layer and the second dielectric layer.

The present disclosure relates to a method of fabricating a semiconductor structure, the method includes forming an opening and depositing a metal layer in the opening. The depositing includes performing one or more deposition cycles, wherein each deposition cycle includes flowing a first precursor into a deposition chamber and performing an ultraviolet (UV) radiation process on the first precursor. The method further includes performing a first purging process in the deposition chamber to remove at least a portion of the first precursor, flowing a second precursor into the deposition chamber, and purging the deposition chamber to remove at least a portion of the second precursor.

The present disclosure provides semiconductor device and methods of forming the same. A semiconductor device according to the present disclosure includes a gate structure, a source/drain feature adjacent the gate structure, a dielectric layer disclosed over the gate structure and the source/drain feature, a gate contact disposed in the dielectric layer and over the gate structure, and a source/drain contact disposed in the dielectric layer and over the source/drain feature. The dielectric layer is doped with a dopant and the dopant includes germanium or tin.

A method of promoting adhesion between a dielectric layer of a semiconductor device and a metal fill deposited within a trench in the dielectric layer, including performing an ion implantation process wherein an ion beam formed of an ionized dopant species is directed into the trench at an acute angle relative to a top surface of the dielectric layer to form an implantation layer in a sidewall of the trench, and depositing a metal fill in the trench atop an underlying bottom metal layer, wherein the metal fill adheres to the sidewall.

A structure includes a transistor including a first source/drain region, a source/drain contact plug over and electrically coupling to the first source/drain region, and a via over and contacting the source/drain contact plug. The via has a bottom portion having a first length, and an upper portion having a second length. The first length is greater than the second length. Both of the first length and the second length are measured in a same direction parallel to a top surface of the source/drain contact plug.

A method for forming a semiconductor structure includes the steps of providing a substrate having a first region and a second region, forming a plurality of semiconductor devices on the first region of the substrate, forming a planarization layer on the substrate and covering the semiconductor devices, wherein the planarization layer on the first region and the planarization layer on the second region have a step-height, performing a first CMP process to remove the step height of the planarization layer, and after the first CMP process, performing a curing process to convert the planarization layer into a porous low-k dielectric layer.

A semiconductor device includes a gate structure on a substrate, an offset spacer adjacent to the gate structure, a main spacer around the offset spacer, a source/drain region adjacent to two sides of the main spacer, a contact etch stop layer (CESL) adjacent to the main spacer, and an interlayer dielectric (ILD) layer around the CESL. Preferably, a dielectric constant of the offset spacer is higher than a dielectric constant of the main spacer.

The present application discloses a semiconductor device with air gaps for reducing capacitive coupling between conductive features. The semiconductor device includes a first semiconductor structure including a substrate, a first conductive line positioned above the substrate and including two sides, a first protruding portion positioned on one of the two sides of the first conductive line, a second conductive line positioned adjacent to the first conductive line and including two sides, a second protruding portion positioned on one of the two sides of the second conductive line and face onto the first protruding portion, and an air gap positioned between the first protruding portion and the second protruding portion. A distance between the first protruding portion and the second protruding portion is less than a distance between the first conductive line and the second conductive line.