Systems, devices, and techniques for creating blind annular vias for metallized vias are described. For example, a vortex beam may be applied to an optically transmissive substrate, where the vortex beam may modify a portion of the substrate in an annular shape. The annular shape may extend from a surface of the substrate to a depth that is less than a thickness of the substrate, and the annular shape may have an annular width (e.g., a ring width) that is the same for various diameters of the annular shape. A blind annular via may be formed by etching the modified portion of the substrate, where the blind annular via may include a pillar comprising the same material as the surrounding substrate. In addition, a metallized annular via may be created by filling the blind annular via with a conductive material, and removing a portion of the substrate opposite the surface.

A method includes forming a dielectric layer and forming a metallic conductor at least partially in the dielectric layer. Formation of the metallic conductor at least partially in the dielectric layer includes performing a planarization process. The method further includes treating respective surface areas of the dielectric layer and the metallic conductor, after the planarization process, to modify the respective surface areas of the dielectric layer and the metallic conductor. In one example, the surface treatment is a neutral atom beam treatment.

A method of increasing the resistivity of a silicon carbide wafer includes providing a silicon carbide wafer with a first resistivity, and applying a microwave to treat the silicon carbide wafer. The treated silicon carbide wafer has a second resistivity. The second resistivity is higher than the first resistivity. The microwave treated silicon carbide wafer can be applied in a high-frequency device.

A method of manufacturing a semiconductor device includes forming active fins on a substrate; forming source/drain regions on the active fins on both sides of a gate structure, the gate structure extending in a direction intersecting with a direction in which the active fins extend; forming an etch stop layer on the source/drain regions; forming an interlayer dielectric layer on the etch stop layer; forming a first opening by partially removing the interlayer dielectric layer so as not to expose the etch stop layer; forming an impurity region within the interlayer dielectric layer by implanting a first impurity ion through the first opening; forming a second opening by removing the impurity region so as to expose the etch stop layer; implanting a second impurity ion into the exposed etch stop layer; and removing the exposed etch stop layer.

A method includes etching a dielectric layer to form an opening, with a component of a transistor being exposed through the opening. A spacer layer is formed, and includes a horizontal portion at a bottom of the opening, and a vertical portion in the opening. The vertical portion is on a sidewall of the dielectric layer. An isotropic etch is performed on the spacer layer to remove the horizontal portion, and the vertical portion remains after the isotropic etch. The remaining vertical portion forms a contact plug spacer. A conductive material is filled into the opening to form a contact plug.

The present disclosure provides a method of fabricating a semiconductor structure in accordance with some embodiments. The method includes receiving a substrate having an active region and an isolation region; forming gate stacks on the substrate that extends from the active region to the isolation region; forming an inner gate spacer and an outer gate spacer on sidewalls of the gate stacks; forming an interlevel dielectric (ILD) layer on the substrate; forming a mask layer over the substrate that exposes a portion of the ILD layer and a portion of the outer gate spacer; selectively etching the exposed portion of the outer gate spacer, resulting in an air gap between the inner gate spacer and the ILD layer; and performing an ion implantation process on the exposed portion of the ILD layer to seal the air gap.

Devices and methods of fabricating integrated circuit devices for forming assymetric line/space with barrierless metallization are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate, a dielectric matrix, and a hardmask, the dielectric matrix including a set of trenches etched into the dielectric matrix and a set of dielectric fins comprising the dielectric matrix, wherein the set of trenches and the set of dielectric fins are of equal width; damaging an inner surface of each trench of the set of trenches; etching the damaged material of the trenches removing the damaged material of the dielectric matrix; removing the hardmask; and metallizing the trenches by depositing a metal directly on the dielectric matrix with no barrier between the metal and the dielectric matrix after the etching. Also disclosed is an intermediate device formed by the method.

The present disclosure relates to semiconductor structures and, more particularly, to Through-Silicon Via (TSV) structures with improved substrate contact and methods of manufacture. The structure includes: a substrate of a first species type; a layer of different species type on the substrate; a through substrate via formed through the substrate and comprising an insulator sidewall and conductive fill material; a second species type adjacent the through substrate via; a first contact in electrical contact with the layer of different species type; and a second contact in electrical contact with the conductive fill material of the through substrate via.

Methods of forming a semiconductor device are provided. A method according to the present disclosure includes forming, over a workpiece, a dummy gate stack comprising a first semiconductor material, depositing a first dielectric layer over the dummy gate stack using a first process, implanting the workpiece with a second semiconductor material different from the first semiconductor material, annealing the dummy gate stack after the implanting, and replacing the dummy gate stack with a metal gate stack.

A semiconductor structure includes a source/drain (S/D) feature disposed in a semiconductor layer, a metal gate stack (MG) disposed in a first interlayer dielectric (ILD) layer and adjacent to the S/D feature, a second ILD layer disposed over the MG, and an S/D contact disposed over the S/D feature. The semiconductor structure further includes an air gap disposed between a sidewall of a bottom portion of the S/D contact and the first ILD layer, where a sidewall of a top portion of the S/D contact is in direct contact with the second ILD layer.