Disclosed are a semiconductor device and a method of fabricating the same. The device includes an FEOL layer, which includes a plurality of individual devices, on a substrate, and first, second, and third metal layers sequentially stacked on the FEOL layer. The second metal layer includes an interlayer insulating layer and an interconnection line in the interlayer insulating layer. The interconnection line includes a lower via portion electrically connected to the first metal layer, an upper via portion electrically connected to the third metal layer, and a line portion between the lower via portion and the upper via portion. A line width of an upper portion of the interconnection line gradually decreases in a vertical direction away from the substrate, and a line width of a lower portion of the interconnection line gradually increases in a vertical direction away from the substrate.

An interconnect structure including a top via with a minimum line end extension comprises a cut filled with an etch stop material. The interconnect structure further comprises a line formed adjacent to the etch stop material. The interconnect structure further comprises a top via formed on the line adjacent to the etch stop material, wherein the top via utilizes the etch stop material to achieve minimum line extension.

A semiconductor structure includes: a base; a first conductive layer, having a portion located within the base and a remaining portion protruding above the base; a barrier layer on the base and at least on a sidewall of the first conductive layer protruding from the base; a dielectric layer on the barrier layer; and a second conductive layer penetrating the dielectric layer and the barrier layer, in contact with the sidewall of the barrier layer, and in contact with at least a portion of the upper surface of the first conductive layer.

A semiconductor chip includes a device layer on a substrate, the device layer including a plurality of semiconductor devices; a wiring structure and a lower inter-wiring dielectric layer each on the device layer, the lower inter-wiring dielectric layer surrounding the wiring structure and having a lower permittivity than silicon oxide; an upper inter-wiring dielectric layer arranged on the lower inter-wiring dielectric layer; an isolation recess arranged along an edge of the substrate, the isolation recess formed on side surfaces of the lower and upper inter-wiring dielectric layers and having a bottom surface at a level equal to or lower than that of a bottom surface of the lower inter-wiring dielectric layer; and a cover dielectric layer covering the side surfaces of the lower and upper inter-wiring dielectric layers and the bottom surface of the isolation recess.

The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.

A semiconductor device includes conductive structures formed in a first dielectric layer, a conductive cap layer selectively positioned over the conductive structures and the first dielectric layer with a top surface and sidewalls, a second dielectric layer selectively positioned over the first dielectric layer and disposed between the sidewalls of the conductive cap layer, a third dielectric layer selectively positioned over the second dielectric layer and disposed between the sidewalls of the conductive cap layer, a fourth dielectric layer arranged over the conductive structures and the third dielectric layer, and an interconnect structure formed in the fourth dielectric layer. The interconnect structure includes a trench structure and a via structure that is positioned below the trench structure and connected to the trench structure. The via structure includes a first portion positioned over the conductive cap layer and a second portion disposed over the first portion and the third dielectric layer.

A semiconductor structure includes a first dielectric layer, a first metallic feature over the first dielectric layer, an air gap over the first dielectric layer and adjacent to the first metallic feature, a second dielectric layer disposed above the air gap and on a sidewall of the first metallic feature, and a third dielectric layer disposed above the air gap and on a sidewall of the second dielectric layer. A lower portion of the first metallic feature is exposed in the air gap. The third and the second dielectric layers are substantially co-planar.

A semiconductor device may include a substrate including an active pattern extending in a first direction, a gate electrode running across the active pattern and extending in a second direction intersecting the first direction, a source/drain pattern on the active pattern and adjacent to a side of the gate electrode, an active contact in a contact hole exposing the source/drain pattern, an insulating pattern filling a remaining space of the contact hole in which the active contact is provided, a first via on the active contact, and a second via on the gate electrode. The active contact may include a first segment that fills a lower portion of the contact hole and a second segment that vertically protrudes from the first segment. The first via is connected to the second segment. The insulating pattern is adjacent in the first direction to the second via.

A semiconductor structure and method for forming a semiconductor structure includes formation of a recess in a metal layer during the fabrication process to provide process improvements and a conductive via with reduced contact resistance. The semiconductor structure includes a dielectric layer, a metal layer, an etch stop layer, and a conductive via. The top surface of the dielectric layer extends above a top surface of the metal layer, and a bottom surface of the conductive via extends below the top surface of the dielectric layer.

An integrated circuit (IC) device includes a conductive region including a first metal on a substrate. An insulating film is on the conductive region. A conductive plug including a second metal passes through the insulating film and extends in a vertical direction. A conductive barrier pattern is between the conductive region and the conductive plug. The conductive barrier pattern has a first surface in contact with the conductive region and a second surface in contact with the conductive plug. A bottom surface and a lower sidewall of the conductive plug are in contact with the conductive barrier pattern, and an upper sidewall of the conductive plug is in contact with the insulating film. The conductive barrier pattern includes a vertical barrier portion between the insulating film and the conductive plug, and the vertical barrier portion has a width tapering along a first direction away from the conductive region.